With upstream commit 649f5c842b ("usb: dwc3: core: Host wake up
support from system suspend"), if the device set to wakeup capable,
dwc3_resume_common() will skip core init that would be caused the
device reset failed after PM resume time.
The above upstream changes also delete the wake up flag set in
dwc3_runtime_suspend()/dwc3_runtime_resume(), so keep in line with it.
Change-Id: If5f06c0d19e123cf907f0fc3294a6ba708a8fd35
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Previously, in commit a811f07f45 ("usb: host: xhci: skip phy init
quirk can configure in dt"), Rockchip added "quirk-skip-phy-init"
quirk to configure the property in DT, however, upstream commit
8e10548f7f ("Revert "usb: host: xhci: mvebu: make USB 3.0 PHY
optional for Armada 3720") changed the condition later that makes
the quirk became ineffectual. So fix it.
Fixes: a811f07f45 ("usb: host: xhci: skip phy init quirk can configure in dt")
Change-Id: If5acf77731532ab6bb19098ac8d435aaeb0b3a10
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rockchip,clk-trcm = <1> to rockchip,trcm-sync-tx-only
rockchip,clk-trcm = <2> to rockchip,trcm-sync-rx-only
remove rockchip,clk-trcm = <0> because of it's the default
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I3c9756d17f9d61360688848ede695c06912b50dc
rockchip,clk-trcm = <1> to rockchip,trcm-sync-tx-only
rockchip,clk-trcm = <2> to rockchip,trcm-sync-rx-only
remove rockchip,clk-trcm = <0> because of it's the default
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I10938cb1eec02456e86c775113bb83ec329390e4
Use the definition of MEDIA_BUS_FMT_XXX instead of the
definition of sii902x_bus_format.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I72b4d92a1704f98f437a80d2a8afe16d9f6b003f
When IRQ BALANCING is enable, the log below is show:
fiq_debugger:cpu 0 not responding,reverting to cpu 6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ic5a1786ecb72dc4b28e9b9fa8428065e111e55ee
[2.353901] rk-pcie 3c0000000.pcie Link up. LTSSM is 0x1
[2.354036] rk-pcie 3c0000000.pcie: PCI host bridge to bus 0000 :00
[2.354058] pci_bus 0000:00: root bus resource [bus 00-0f]
[2.354074] pci_bus 0000:00: root bus resource [??? 0x4000000-0xf40fffff flags 0x0]
...
The original link event is checking LTSSM and ensure it's in L0. However
enabling ASPM will make accessing config space failed. So commit
824c99261a ("PCI: rockchip: dw: Update link up check state") remove the LTSSM
check. But it introduce a situation that if link still in training and host
bridge tries to enumerate slot, it will fail unexpectedly. Fix this by removing
rk_pcie_link_up and let dwc core use its own port logic to decide the link state.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I41f05a8aa89ac33782d569ffa7d466cf95981c68
* commit '0eba9f8ec037e4c7fccb16e2a433be822dd802b8':
dmaengine: pl330: Add support for interleaved transfer
Merge using ours merge strategy.
Change-Id: I466ab3dfd0b08e5dea4cc62f8cf9c1a0bc631653
The pins of gt1x and sii9022 are multiplexed.
In addition, add support for bt656 by the same display
ext board.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9164bd0a354a215cf5e04eec99946714c0638465
This patch add support for interleaved transfer which used
for interleaved audio or 2d video data transfer.
for audio situation, we add 'nump' for number of period frames.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I502ea9c86c8403dc5b1f38abf40be8b6ee13c1dc
* commit 'de0064df8fa35b0d0e2951b2b2799f9e02157439':
arm64: dts: rockchip: rk3308b-amp: using 64-bits for cpu's affinity
arm64: dts: rockchip: rk3562-amp: using 64-bits for cpu's affinity
irqchip/gic: add the parameter of gic version for rockchip amp
soc: rockchip: amp: using 64-bits variable to manage the cpu's affinity
irqchip/gic: allow to config pending function between different os
arm64: dts: rockchip: rk3588-vehicle-evb-v22: Add delay for all camera related regulators
drm: bridge: dw-hdmi: Fix 3d fp mode clock miscalculation
BACKPORT: xhci: Improve the XHCI system resume time
media: rockchip: isp: fix rv1106g3 4k cmsk right
Change-Id: I253ac2ecaee64e1b90cd2f2fb85538ad5b77da65
[2.353901] rk-pcie 3c0000000.pcie Link up. LTSSM is 0x1
[2.354036] rk-pcie 3c0000000.pcie: PCI host bridge to bus 0000 :00
[2.354058] pci_bus 0000:00: root bus resource [bus 00-0f]
[2.354074] pci_bus 0000:00: root bus resource [??? 0x4000000-0xf40fffff flags 0x0]
...
The original link event is checking LTSSM and ensure it's in L0. However
enabling ASPM will make accessing config space failed. So commit
824c99261a ("PCI: rockchip: dw: Update link up check state") remove the LTSSM
check. But it introduce a situation that if link still in training and host
bridge tries to enumerate slot, it will fail unexpectedly. Fix this by removing
rk_pcie_link_up and let dwc core use its own port logic to decide the link state.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I41f05a8aa89ac33782d569ffa7d466cf95981c68
The PLDO6 must be always on. if the PLDO6 is off, the PMIC
will be abnormal.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I5c2cf8f0d2ba3cb08cd7538d998857d8c2db55f2
In the display-serdes panel driver, it has the same name
"serdes-panel" as rkserdes panel device. When register
rkserdes panel device, it may mismatch to the display-serdes
panel driver. To avoid this issue happen, change the rkserdes
panel device name. For the same reason, change the rkserdes
panel driver name.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic146472c40252b3e55b2d46f1a6bfd099eb013c3
1. There are two rkvenc cores and share a iommu domain. When they work at
the same time, the arg with iommu fault handle will be mismatch with
real device.
So find the real device according to iommu_dev.
2. config appropriate timeout threshold and it can trigger hw timeout
when pagefault.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: If816e43c9732d6cefc60d80efbaf297001d500ff
add private v4l2 event: RK_HDMIRX_V4L2_EVENT_AUDIOINFO
when audio info changed, driver will queue event and apps
should chang audio record parameters
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I6fa6c951d648f546655475eede21d1769444741c
If the scl has been pulled low for a long time and is not released,
at this time, because the exception needs to end the I2C, a reset
needs to be done to ensure that the state machine is restored. Set
the timeout time to 200ms, and the debounce of the scl is pulled
low to 100ms.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iee0c2afe2fbd59a30d1b7ef486d0856b00b88cc8
If autostop mode is enabled, such as RK3588, autostop mode requires
statistics on the transmission length; for tx only mode, the device
address is also counted as one byte, so the judgment conditions become
different.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I91c0b68fabb60952f630a98133423aa4cb1b9b48
