The USB 3.0 PHY need to config grf when change between
USB 2.0 only and USB 2.0/3.0 mode, so we add grf property
for u3phy node.
Change-Id: I4ff2670d0637e9d0cbae06f5e9efbde9a8513bb3
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch create host_testmode file in debugfs for
USB HOST. It's useful for us to use a scope to verify
signal integrity for USB2/USB3 HOST.
For example, set testmodes for rk3328 board USB:
1. set test packet for the USB2 port of USB3 interface:
echo test_packet > /sys/kernel/debug/usb.23/host_testmode
2. set compliance mode for the USB3 port of USB3 interface:
echo test_u3 > /sys/kernel/debug/usb.23/host_testmode
3. check the testmode status:
cat /sys/kernel/debug/usb.23/host_testmode
The log maybe like this:
U2: test_packet /* means that U2 in test mode */
U3: compliance mode /* means that U3 in test mode */
Change-Id: I6ddead14a7b78a011bbffcec6bf865df0632fe1b
Signed-off-by: William Wu <wulf@rock-chips.com>
The Inno USB3 PHY disable the ability to toggle the CP test
pattern by default. But when do do USB3 compliance test, it
need to change the CP test pattern according to the requirement
of oscilloscope.
This patch add phy_cp_test function to enable the USB3 PHY
to detect the negative pulse which from the Aux Out of the
oscilloscope in SSRX+, and then the USB3 PHY can toggle the
CP test pattern while do USB3 compliance test.
Change-Id: Idbdf937a7a032dcedfd5f207b2d6d5961ed27b15
Signed-off-by: William Wu <wulf@rock-chips.com>
There are several SoCs (e.g. rk3228h and rk3328) that integrated
with Inno USB3 PHY, they can't toggle CP test pattern when do
USB3 compliance test by default.
This patch add a cp_test callback for USB3 controller to enable
the special USB3 PHY to toggle the CP test pattern.
Change-Id: I2d603202723a4c044d4231af10cfe2c60ec0e988
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch tries to get the USB3 PHY using, and associates
the XHCI shared_hcd device with it.
With this patch, the USB HUB core driver can do USB PHY
operations base on USB PHY framework, e.g. call usb_phy_
notify_connect() or usb_phy_notify_disconnect() to notify
USB PHY driver to do soft connect or soft disconnect.
Change-Id: I3b51181b840a68ae477b764013446f49dbf7ca70
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds a quirk to disable rk3328 xHCI controller
USB3 port autosuspend function, and USB2 port autosuspend
function is still enabled.
Change-Id: Ie5e6883811b09a9a0d839ce59d8f9c4ad8ad3378
Signed-off-by: William Wu <wulf@rock-chips.com>
Some xHCI controllers (e.g. Rockchip rk3328 SoC) integrated
in DWC3 IP, don't support USB 3.0 autosuspend well, so we
need to disable USB 3.0 HUB autosuspend function with a quirk.
Change-Id: I72d93837496f875dbcbb16818aa3690017cc1085
Signed-off-by: William Wu <wulf@rock-chips.com>
Some USB controllers (such as rk3328 SoC DWC3 controller with INNO
USB 3.0 PHY) don't support autosuspend well, when receive remote
wakeup signal from autosuspend, the Port Link State training failed,
the correct PLC is Resume->Recovery->U0, but when the issue happens,
the wrong PLC is Resume->Recovery->Inactive, cause resuming SS port
fail. This issue always occurs when connect with external USB 3.0 HUB.
This patch add a quirk to disable autosuspend function, and add new
'usb3_disable_autosuspend' member in xHCI platform data to support
set the quirk based on platform data.
Change-Id: Ice01d70178206e22658660361dd3a525046cbcf5
Signed-off-by: William Wu <wulf@rock-chips.com>
Some USB host controller seems to have problems with
autosuspend. For example, Rockchip rk3328 SoC USB 3.0
wouldn't handle remote wakeup correctly with external
hub after entered autosuspend, caused to resume SS
port fail.
This patch introduces a new quirk flag for hub that
should remain disabled for autosuspend.
Change-Id: I6d14222b2c5025583fea811a6afd6abd22f41cb9
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch enable otg-port node of usb2-phy for dwc2 otg controller
on rk3328-evb board.
Change-Id: Ic6ce4beb2ba1814554e709a7d8af83a9ece9d7c9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds otg-port node of usb2-phy for dwc2 otg controller
on rk3328 SoC.
Change-Id: I4cda3e02d9cab2328cb2a3fe423cd4198258e32b
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds otg-port configuration for rk3328 SoC.
Change-Id: Ic680c7f345396c129e7b2ea8a8dded8ba6ee0ae9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
1. codec into bias off mode when secondary standby
2. restore hw registers during a suspend/resume cycle.
(Note: codec power must be closed after suspend)
Change-Id: I530d59c161afa64bb2781bc12228ff3b60debd6f
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
The md5sum is identical after rename, so this commit is safe.
Change-Id: I97cb5faecebaad9d2e9c39f67f19f662642cc5e8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Except dts of VR.
The md5sum is identical after rename, so this commit is safe.
Change-Id: I9ec324355ae67bbe2bb626090402ae797de13d92
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Add otg-vbus-gpios optional property to assigned a gpio to
control vbus of otg port.
Change-Id: I257a53edc4d62543f8ac9c7591c29e7231227c20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The current code of u2phy set vbus level by set cable state of power
controller, so we can't control vbus level if the platform use gpio
to control vbus. This patch add gpio in u2phy driver and set vbus
level if the mode of usb is detect by u2phy.
Change-Id: I84e966b6e24cb9b6a199fcaad0c509fc003089de
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
disable spdif support which is useless meanwhile
Change-Id: Ib116bac82d5d3d13392be2fb62eaf978a08592a0
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
Along with a slight modification in mali_kbase_core_linux.c,
for building in rk Linux 4.4:
-#if KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE
+#if KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE
Change-Id: I34565cb975866b46c5e3a4d8e2ac5e350dcceb80
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
This patch add a rockchip specific glue layer to support
USB 3.0 HOST only mode for rockchip USB 3.0 core wrapper
consisting of USB 3.0 controller IP from Synopsys and USB
3.0 PHY IP from Innosilicon.
With this patch, we can support for XHCI integrated in
DWC3 IP on rockchip platforms. Because some INNO USB 3.0
PHY can't detect disconnection by PHY IP, and cause USB3
device unrecognized when replugged again. So we depend on
the HUB core driver to detect the disconnection, and send
notifier to DWC3 driver from USB PHY driver, then we can
do phy reset and remove/add hcd to reinit HCD.
Change-Id: I6972c6f9f8f7160dbd74ad531b843a65ccec5dc0
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds the devicetree documentation required for Rockchip
USB 3.0 core wrapper consisting of USB 3.0 controller IP from Synopsys
and USB 3.0 PHY IP from Innosilicon.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Change-Id: Ia240627c31cd3ff2f2d7f1a1faa9c7d88207d04f
Signed-off-by: William Wu <wulf@rock-chips.com>
The rk322xh USB3 PHY has a problem to detect disconnection,
it loses the ability to detect an absence of a far-end
receiver termination specified in USB3 spec Table 6-21,
and this causes the linkstate to change between SS.Inactive
and Polling state, but not return to correct state Rx.detect.
To workaround this bug, we depends on the hub_event to
detect the port linkstate change and do soft disconnect.
And then do USB3 PHY reset and reinit HCD to recovery
the whole USB3.
The workaround process is:
Plug out USB3 device -> hub_event detect PLC and find
USB 3.0 port in the Inactive -> call usb_remove_device()
to do soft disconnect -> call usb_phy_notify_connect()
-> send notifier to DWC3 controller driver to do USB3
PHY reset and reinit HCD.
Change-Id: Icb975581c6fbbb34a7da90ddca47e04a46e5da48
Signed-off-by: William Wu <wulf@rock-chips.com>
Some rockchip SoCs (e.g. rk322xh/rk3328) integrated with
INNO USB 3.0 PHY have a problem to detect disconnection
correctly. So we need to depend on the usb phy framework
to handle the disconnection.
Change-Id: Ie3bd015c89e1fb8d46f69fe8d274e29462bfb763
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch implements a USB 3.0 PHY driver for Rockchip
platform (e.g. rk3328) with Innosilicon IP block.
Change-Id: Ia6ed5df6b7b9eecebd5a5c8a4c4a6df7d26b7422
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds USB 3.0 PHY grf node and apb node
for rk3328 USB 3.0 module.
Change-Id: I9d4e6c6d6792ac5fd6c2a4d7cc902f1ff0cf4ef1
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds a binding that describes the Rockchip USB 3.0
PHY designed by Innosilicon.
Change-Id: Ia5b9f18743c7a7ed1b9d33420608a2f12a086aee
Signed-off-by: William Wu <wulf@rock-chips.com>
