From the TRM, the MIC PGA gains for 8 ADCs:
- version A:
0dB, 20dB
- version B:
0dB, 6.6dB, 13dB, 20dB
Change-Id: I9cf758708ec80afe06340f48a2f71f24654f36fe
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rk817/rk809 must restore the PMIC_POWER_EN OTP value before the system reboot.
Change-Id: I2ccfbb4d47eb41cdcea048111873b6ab85477d64
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
rk3308k supports wide temperature feature, it makes system suspend
stable in extrem low temperature.
Change-Id: I07427c21263e5a48bc07c935291f8494e50ec9e3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
The dwc3_rockchip_probe() spends lots of time to initialize
the dwc3 host and pm runtime. It significantly lengthen the
boot time.
I test on RK3399 Excavator Board, the execution time of the
dwc3_rockchip_probe() on Type-C0 is about 220ms without this
patch (Type-C0 connect to PC USB port at the same time). Most
of the time is spent on remove hcd(~16ms) and pm runtime
suspend (~180ms).
1. remove hcd (~16ms)
When do usb_remove_hcd(), the xHCI should wait 16ms to
enter the stopped state with the following log:
xhci-hcd xhci-hcd.11.auto: Host not halted after 16000 microseconds
2. pm runtime suspend (~180ms)
Race condition is observed during pm runtiem suspend.
CPU0 CPU1
---- ----
rockchip_chg_detect_work() pm_runtime_suspend
-> mutex_lock(&rport->mutex) -> dwc3_runtime_suspend()
|| -> dwc3_suspend_common()
\/ -> dwc3_core_exit()
USB_CHG_STATE_UNDEFINED -> phy_power_off(dwc->usb2_generic_phy)
|| -> rockchip_usb2phy_power_off()
\/(100ms) -> wait for rport->mutex
USB_CHG_STATE_WAIT_FOR_DCD .
|| .
\/(40ms) .
USB_CHG_STATE_DCD_DONE
||
\/(40ms)
USB_CHG_STATE_PRIMARY_DONE
-> mutex_unlock(&rport->mutex)
-> mutex_lock(&rport->mutex)
This patch runs the remove hcd operation and pm runtime
suspend in an async_domain to speed up the boot time. With
this patch, the dwc3_rockchip_probe() spends only ~12ms.
Change-Id: Ic60774e5c3e7be9f718c18ade86b2d95a9134b4c
Signed-off-by: William Wu <william.wu@rock-chips.com>
Split DT source files to separate out android firmware for Android Pie & Oreo
Change-Id: Ib16858996e236bb292bc380c0fddea2f5213c15b
Signed-off-by: wu jingchen <oven.wu@rock-chips.com>
The Seagate Expansion Portable Drive HDD (ext4 file system,
idVendor=0bc2, idProduct=2321) is reported to fail to work
on the rk3399/rk3328 platforms USB 3.0 interface with the
following error message when do read/write operation by dd
command:
xhci-hcd xhci-hcd.11.auto: Ring expansion failed
It's because that xHCI use the dma_pool_alloc() to allocate
DMA buffer for segment_pool with GFP_ATOMIC flag, however,
the default 256 KiB coherent pool is too small for the USB
HDD, so increase it to 1024 KiB to make sure that devices
will be able to allocate their DMA buffers with GFP_ATOMIC
flag.
Change-Id: Ic94c9ceeeb4adabe860af46546550aa8f73f11ca
Signed-off-by: William Wu <william.wu@rock-chips.com>
Set CPU voltage to low temperature voltage before system suspend,
so that it can resume successfully at low temperature.
Change-Id: Ib9ab16558ff69ea80e862473ef9ec6bfa7cd61ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If support wide temperature, it necessary to set voltage to low temperature
voltage before system suspend, so that it can resume successfully at low
temperature.
Change-Id: Ie6787092c9510788054217bd830b5ae1e4dd6bc2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Because uart does not have high requirements
for the clk Jitter, the fractional frequency
divider does not need to meet the 20-fold relationship.
(If uart clk rate < 24M,Use 24M as the fractional
clock source.)
Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Numerator is greater than 4,the clk jitter is better.
Change-Id: I9fda9ddeb7b26c6b8559b4126e2ad1d29bb850d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
ROCKCHIP_DRM_DEBUG will call API from debugfs, need to select DEBUG_FS.
Change-Id: I06a7c7c2ce9179796e551727fdd2e08313bfe6ff
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The referenced voltage is not changed after initiation, so just only
get referenced voltage once.
Change-Id: I1eeab03f68855fafe010db328ec7bbcfa7d52310
Signed-off-by: David Wu <david.wu@rock-chips.com>
from isp specification, only semi-planar with
uv swap.
Change-Id: I3fc713cd6cbab1e12a94d7b8144d7d43a6de5530
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
sp rgb888 format is bgrx 32bit in memory, change to BGRX.
sp rgb666 format is 2bit unused + 6bit data as b/g/r,
append 1bits unused, 32bit in memory, no V4L2 format
apply to it, so delete it.
Change-Id: Iff8c2e560030d76b26d81faff19a3bd49ca33643
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Since the mali.ko is *not* upgraded by userspace, rk3399 linux hope keep
mali driver version is the same with userspace.
Change-Id: Id5af615f1f7b0c95587bc5faeeeff35251797e1a
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
In addition, enable CONFIG_MALI_MIDGARD and disable CONFIG_MALI_BIFROST
for rk3399.
Linux devices of rk3326 or px30 have their own defconfig files,
unlike Android devices.
Change-Id: I8bd8c10fad78f5a6a83d1fdd9e99850dda49ac47
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The process to get current source code under midgard_for_linux/ :
1. On the status of commit 18166b65,
revert commit "91842c9 MALI: rockchip: upgrade midgard DDK to r18p0-01rel0",
which upgraded drivers/gpu/arm/midgard/ from DDK r14 to r18.
2. copy directory drivers/gpu/arm/midgard/ to drivers/gpu/arm/midgard_for_linux/.
It's ensured that changes of commits in drivers/gpu/arm/midgard/
from RK power management group early than commit 18166b65
are correspondingly remained in current drivers/gpu/arm/midgard_for_linux/.
Change-Id: I41463a8c160e5d25365d6872eef1049de4a317fb
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The ATF must contain the following commit:
cd61876e275e ("plat: rk3399: ddr: add support adjust noc read latency")
Change-Id: I322f8c9d454fb1234b042438c85521275ceda4bc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
