As the Dan report the smatch check the thermal driver warning:
drivers/thermal/rockchip_thermal.c:551 rockchip_configure_from_dt()
warn: impossible condition '(thermal->tshut_temp > ((~0 >> 1))) =>
(s32min-s32max > s32max)'
Although The shut_temp read from DT is u32,the temperature is currently
represented as int not long in the thermal driver.
Let's change to make shut_temp instead of the thermal->tshut_temp for
the condition.
Fixes: commit 437df2172e
("thermal: rockchip: consistently use int for temperatures")
Change-Id: I7951bf83baec2ef0ae8fe50d5735f992a7d3ed41
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3399 SoCs have two Temperature Sensors, channel 0 is for CPU.
channel 1 is for GPU.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit b0d70338bc)
Change-Id: I12bccb3c4a56c56f16a019c3faad909bfae65b97
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The RK3228 SoCs has one Temperature Sensor, channel 0 is for CPU.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 7b02a5e782)
Change-Id: I45def60892a8f5cd6fd18ad064b4bf7c13260b59
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
the calculation use a global table, not their own table.
so adapt the table to the correct one.
Change-Id: Id416e41910de297259a85a3ae06f4cc3c5788035
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.
On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.
To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.
The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.
Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
commit 5035981979)
Change-Id: I382323c61f94e79ee7eaec6db16f6c2a9ad387eb
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 9c4d6e5537)
Change-Id: I3a4aa2eb470976d69fef6b4fc2a33d9b46989817
Populates regulator_init_data structure by extracting data from device
tree node, when regulator drivers register a regulator. so we don't
repeat it.
Change-Id: I481e7c802a24916f15c5b3a5eaf66f32dc0272d7
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Backward compatibility with develop-3.10 except for
3dmode, which rename to mode3d.
Change-Id: I9dea6d25adc18c5e1580078f574fa44690791a33
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Since HDMI needs clock rate 74.25MHz, so plls must support
a multiple of it.
For Rockchip rk3368 pll has better jetter with 1188MHz, so
add 1188MHz support.
Change-Id: I68c7333ae076ecabf8637298ee8ca43149cb17d1
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Add "assigned-clocks" for rk3368 cru node, to intalize
clock rate for plls, bus and peripher.
Change-Id: Ic36401fef73b005d778b8ccc8527633af408985c
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit e8099067de)
Change-Id: I1e7b75eba06fbe27079c3887170ce801da005ce0
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 0bbe62eb92)
Change-Id: I3deed226430c492dc3b70337ae3e89d201aeb66d
The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit d566ebc3c0)
Change-Id: Ia0530f4e00c8ea15420b49587097f07ac1af5092
The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 0f28d98463)
Change-Id: Ie7e8f1e7d6de5e149705cc5f6d6207e839eca2bd
Similar to commit 9880d4277f ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.
And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit c6d5fe2ca8)
Change-Id: If85678467e8dc4b4cfce07c3d31faf0c11479780
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.
Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
commit 535ebd428a)
Change-Id: I26364fdba8cdfe36c8b9ba767b4226c9ac6ff118
This patchset attempts to new compatible for thermal founding
on RK3228/RK3399 SoCs.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 4be02530fc)
Change-Id: I9fd1f52d7b4781230e5436e90ed6d9d2c95d06cb
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patchset trys to dictate unified format for driver.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 13c1cfda1a)
Change-Id: I9659ae150c9d24f2482fd8c285dcfeb65bf873b1
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Add the devicetree binding for the cru on the rk3366 which quite
similar structured as previous clock controllers.
Change-Id: I109da26f88cd733b64d4c4339db63346dd9ffea6
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Add the dt-bindings header for the rk3366, that gets shared between
the clock controller and the clock references in the dts.
Change-Id: Ie4d8f9d02be2331b368d44f5d76a92fd9959b72a
Signed-off-by: Xiao Feng <xf@rock-chips.com>
Skip the update_reg_update when vop is suspend, because
register access would hang up the system when vop is suspend.
Change-Id: I01e712736df9a6de88440ee67c624a26ea752d85
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
