Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Change-Id: I5d341cac64581cd39ced0703054a70fd1eacc4a6
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Currently dp83867 driver returns error if phy interface type
PHY_INTERFACE_MODE_RGMII_RXID is used to set the rx only internal
delay. Similarly issue happens for PHY_INTERFACE_MODE_RGMII_TXID.
Fix this by checking also the interface type if a particular delay
value is missing in the phy dt bindings. Also update the DT document
accordingly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 34c55cf2fc)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: Ideca1aae2512f0ee2944bc751e47436d8d1746b6
Add documention of ti,min-output-impedance and ti,max-output-impedance
which can be used to correct MAC impedance mismatch using phy extended
registers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit d6081de7e0)
Change-Id: I5e1f90caff7fee13369302a84d1dac370cb75f5e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Change-Id: I416afa8ef29d9a684068fa880f99ca7b720cfd14
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.
Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ac6e058b75)
Change-Id: I1b17b6c88e76230fde3fd1c93c3bb09ee0c2790d
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit fc6d39c395)
Change-Id: Iea19a3e02a5072e5b3ab2b4ee33befd5805100e2
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
programmed as an interrupt output instead of a Powerdown input in
Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
current driver doesn't do this and as result IRQs will not be generated by
DP83867 phy even if they are properly configured in DT.
Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
driver will work properly in interrupt enabled mode.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 5ca7d1ca77)
Change-Id: Ic4fd8e84a2e41f217850230699e00f603ea3f086
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Add support for programmable MAC impedance configuration
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ed838fe937)
Change-Id: I189307e95ccb4f71a245ec69df6f4ab0b32130ec
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
When initializing the PHY control register, the FIFO depth bits are
written without reading the previous register value, i.e. all other
bits are overwritten with zero. This disables automatic MDI-X
configuration, which is enabled by default. Fix initialization by doing
a read/modify/write operation.
Signed-off-by: Stefan Hauser <stefan@shauser.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit b291c41817)
Change-Id: If14021286ff6e8b770f6cfe0f4026e29414e75d8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The address of the device can be determined from the phydev structure,
rather than passing it as a parameter.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 053e7e1692)
Change-Id: Ib0f855bb2f6ad38e37c030343d6ccb1cc8848178
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Device tree properties for a phy device are expected to be in the phy
node. The current code for the DP83867 also tries to look in the
parent node. The devices binding documentation does not mention this,
no current device tree file makes use of this, and it is not behaviour
we want. So remove looking in the parent device.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 7bf9ae016e)
Change-Id: Ia0b9f5fbe15b3c042880b8c8712c1b72f994029e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This patch adds the supporting to the eDP panel sold by
the T-CHIP for the Firefly RK3288. I assign the VOP lite
for the eDP panel and VOP big to HDMI, as the HDMI supports
4K resolution. With a different VOP device, eDP panel
and HDMI could display a different contents.
The InvenSense MPU6050 sensor at the botton of the panel
is also enabled.
The Firefly RK3288 Reload use a different GPIO pin to enable
the power of the eDP panel.
Change-Id: Id78249f001d171ede79fe835d24c40a75ff8a0df
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
ATM dwmac-rk will always set and enable it's internal delay lines.
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.
Tested only with a RK3288 based board.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eaf70ad14c)
Change-Id: Id0152a9f048cbc810b62c252d4105594ed1895df
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.
This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).
(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>
When do reboot test with otg cable plugging in, it may
casue two issues: 1. system hung when access grstctl reg
in dwc_otg_core_reset(); 2. kernel panic when remove the
host channel from the free list in assign_and_init_hc().
This patch adds 1.5~2ms delay afer resume USB2 PHY, the
time for utmi_clk provided from USB2 PHY to stabilize,
and then we can access the usb core registers safely, it
can avoid system hung.
Also, we avoid to call otg20_hcd_connect_detect() if dwc2
is host mode except force host mode during probe, because
we will do the same work in check_id_work() later. This can
fix the issue that init usb core and host twice when boot
with otg cable and usb device, which may cause kernel panic
because of hc list is NULL.
Change-Id: I35aa36762c64b14b580b493d213610379676ab56
Signed-off-by: William Wu <william.wu@rock-chips.com>
If the system rebooted, there might be i2c transfer at the
same time, it will make something unpredictable, because
the i2c host was reseted, but the slave device wasn't, such
as rk808 pmic, so make sure the i2c transfer to be finished
before system shutdown at the reset mode.
Change-Id: I3c09f3acbe86595c295edc191aa38351adb7d5dc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
When build with ARM_LPAE enabled:
arch/arm/mach-rockchip/pm.c: In function 'rk3288_init_pmu_sram':
arch/arm/mach-rockchip/pm.c:85:23: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
Change-Id: I526f13439c3c7edde77a27419d488a8f79081661
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The PD policy would take 5-7s to enter PD disabled state (send
50 times caps, the more bytes of caps cmd, the more time it
takes), So we ough to pick usb notify to PD startup state for
better user experience.
Change-Id: I3b2dc1c5df31296520685ba57e892a30ef3c28aa
Signed-off-by: zain wang <wzz@rock-chips.com>
In the spec:
The tTypeCSendSourceCap is defined from 100ms to 200ms.
The nCapsCount is defined 50.
Change-Id: I09bcdb7a83c353ab099d51228cf8ca13e562d839
Signed-off-by: zain wang <wzz@rock-chips.com>
As the PD spec, we ough to tell policy engine if the cable
support PD, some state would run depend on this value.
Change-Id: Ied725ecb53f71a5e367b1ca91acd7f23372c54a1
Signed-off-by: zain wang <wzz@rock-chips.com>
Refer dwc2 databook and programming, the controller automatic
receive SETUP packet to the receive FIFO and respond to Host
ACK whether ep enabled or not. The core internally set the IN
NAK and OUT NAK bits when SETUP packet was received in order
to software process SETUP packet and transition to the next
stage.
If software has not enabled ep before the Host send the SETUP
packet, set enable ep and cnak at the same time the Host send
DATA OUT packet. Then dwc2 controller write the setup data to
the memory and disable ep, respond ACK to the Host DATA OUT
packet. The Host transition to the status stage, but we lost
the DATA OUT packet. So don't set cnak when setup stage, the
dwc2 controller respond NAK to the Host DATA OUT packet, the
Host resend ping packet and DATA OUT packet.
TEST=set gadget work as usb audio and connect to ubuntu(rk3036)
Change-Id: Id791c44baf3d363a975ceaeb7d1c879c9703ce1d
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
when using upstream u-boot load kernel, reserves memory from early
allocator will fail if memory node is not specified.
===============================
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0xf00
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacctdd
...
[ 0.000000] earlycon: Early serial console at MMIO32 0x11030000 (options '')
[ 0.000000] bootconsole [uart0] enabled
[ 0.000000] cma: Failed to reserve 16 MiB
[ 0.000000] Memory policy: Data cache writealloc
This patch fix it.
Change-Id: I6a3c6b1e210bbc9a5240503ab7bf5ddab89910ba
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch fixes the following DTC warnings:
"Node /memory has a reg or ranges property, but no unit name"
Change-Id: I140cef24b80e4ff0b9fbe6f0e07221fba1da72f0
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 09fbc4a08e)
init irq later than workqueue_struct and delayed_work to
avoid NULL ponint
Change-Id: I715296a715cb07149a6dce236a3b8ccafe00622e
Signed-off-by: chenjh <chenjh@rock-chips.com>
Add dfi and dmc nodes in the device tree for the ARM64 rk3368 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.
Change-Id: I155b838a8773ff1842058bebb1ed2747ca8e2e0b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
rk818's input charge voltage limit function doesn't works well. If software
set input current over than charger's max support value, rk818 may cause
charger over current protect which means disconnecting.
To solve this problem, we need to detect vbus voltage by TS2 pin, if vbus
is upper than 4.4v, we can safely adjust input current step by step from
low to high until meeting the target input current value.
Change-Id: I01d63974f251ad8ef0037158b66f4b85d3928baf
Signed-off-by: chenjh <chenjh@rock-chips.com>
due to playback and capture will call startup at the same time
when voip call, but hdmi_codec driver only support playback
[ 51.134149] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[ 51.134179] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[ 51.134197] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22
[ 51.143250] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[ 51.143277] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[ 51.143294] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22
[ 51.157546] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[ 51.157584] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[ 51.157603] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22
Change-Id: I970695dbe19f070579aacd044e6a01c44e687a2e
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
