The main reason to add this check is to avoid unnecessary
mmc_request like the on-going cmd and the corresponding sbc
if the card is removed. Although we have already checked this in
dw_mci_handle_cd for runtime usage of sd card and dw_mci_init_slot
for noremovable devices, but there is a timing gap before it really
calls dw_mci_get_cd as mmc_detect_change needs some delay here.
Another gain here is that we could save some checkings of card status
after sd card been removed.
Change-Id: Iea741c1c72985fbe078f48da3796bddcab816e66
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
dw_mci_get_cd have already dealt with these for
both of internal card-detect and gpio card-detect.
Change-Id: I59eb591d2dace127bae3520d7920056d704ed1e6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The dw_mmc driver enables HLE errors as part of DW_MCI_ERROR_FLAGS but
nothing in the interrupt handler actually handles them and ACKs them.
That means that if we ever get an HLE error we'll just keep getting
interrupts and we'll wedge things.
We really don't expect HLE errors but if we ever get them we shouldn't
silently ignore them.
Note that I have seen HLE errors while constantly ejecting and
inserting cards (ejecting while inserting, etc).
Change-Id: I95fcc4e2d657572b365980794bb941ea39403699
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
We should change HS400 mode selection timing to meet JEDEC
specification. The JEDEC 5.1 said that change the frequency to <= 52MHZ
after HS_TIMING switch. Refer to section 6.6.2.3 "HS400" timing mode
selection:
Set the "Timing Interface" parameter in the HS_TIMING[185] field of the
Extended CSD register to 0x1 to switch to High Speed mode and then set
the clock frequency to a value not greater than 52MHZ.
Change-Id: Ia676b8e3ea4a66867372c9719d768a6d4405ff15
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
It's meaningless to check the card's status which execute
the on-going flush. As the status been responsed make no
any sense here.
Change-Id: I34197d1c93c01337dd2e68ec22e3ce8dd195c424
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Manually merge hs400es from upstream to avoid
too much rework.
Change-Id: I69821c866ba38ead929f437a16618694d92d470c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
1 Remove pd_center because the ddr not allowed to power off the pd_center.
2 If the driver not used the pd. the pd will be offed after genpd init complete.
(pd disable unused)
Change-Id: I66db4df1835a48e3c0f96019bb727994e2516af9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The newer SoCs (rk3366, rk3399) take a different usb-phy IP block (INNO)
than rk3288 and before, meanwhile, most of phy-related registers are also
different from the past, so a new phy driver is required necessarily.
Change-Id: I32320fd516af146ef9b7816d5b167e1b682a659b
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Set status of tsadc node to "okay" to make tsadc work.
Change-Id: I741adc9ce611f6f0f279fbb351dfaa5fc947db06
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
according to our testing results, added the ipa parameters for both cpu
and gpu.
for now,the gpu thermal zone is used only to get the gpu's temperature.
Change-Id: I14274c0b2d7645d08f37d918ddb415ac49ed0d9e
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.
But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit git.kernel.org mmind/linux-rockchip.git
volatile-v4.8-clk/next e3d86c1a2295184374cf25cdb525e68a93b0ff90)
Change-Id: I616846d389d324be529966c63820e8707c7d428f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It maybe due to a copy-paste error the error handing should be
cclk not clk when checking if the cpuclk registration succeeded.
Reported-by: Lin Huang <lin.huang@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/fixes commit df43cf8f1c116f26fcfd89ce9b1119929c732597)
Change-Id: I7d21808194c914e9117c498309e4b69861799318
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
according to our testing results, added the ipa parameters for both cpu
big cores and cpu little cores, and updated the parameters for gpu.
for now,the gpu thermal zone is used only to get the gpu's temperature.
Change-Id: Ifc7708de9d880e0f9cd5da0bb71a135b0c381b45
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
grf_soc_con20 will be reset when vio pd close, so we have to
set hdmi source everytime wake up
Change-Id: I84597265238c1d3057002aad63a0f9b64b99f704
Signed-off-by: xuhuicong <xhc@rock-chips.com>
set armclkb 816M to slove the crash,which reset core voltage below 0.85V.
So make sure the 0.8V voltage is enough for the init clk freq.
Change-Id: I4dba25fdfd610c0751f50ce09283c32a9b3f420f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
this patch make it more reasonable and readable, because when we chose
I2S_CKR_TRCM_TXONLY, we only output clk_lrck_tx, and hardware need to
confirm this signal is wired to external codec lrck_tx/rx at the same time.
for convenience, we just handle lrck_txonly if we enable symmetric_rates
in driver and dai_link. otherwise, we use the separate lrck_tx/rx.
Change-Id: I383c34d2337715148566f7e2ada367f2ee279cb5
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/sound.git topic/rockchip
commit 7ec4a1c34a190297540626dfa240dc033beca196)
Set status of saradc node to "okay", to support saradc.
Change-Id: Ic36e390097efbf564b5cbdc321086b6965cd54b0
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add compat_ioctl for accessory to work on 64-bit platforms.
Change-Id: I805395c35017111bf0c462847f11765c7088d266
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Define a new ioctl for MTP_SEND_EVENT, as its
ioctl numbers depends on the size of struct
mtp_event, which varies in ARCH32 and ARCH64.
Change-Id: I060604057ac6c55991118b3f61b187468b4ee0fd
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/377800
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add compat_ioctl for mtp to work on 64-bit platforms.
Change-Id: Icef0f42a554d770a83152c4185aca9e39e041165
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Rockchip RK3399 SoCs support reboot with modes, such as recovery mode,
loader mode and normal mode.
Change-Id: I96ed872f849c2b3b06d236248995db18be070960
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
It seems than android gcc can't pass gcc-goto.sh check, but asm goto work.
So let's active it.
Change-Id: I75310af8cf3746a5c110daa564e96eeb1d7f1070
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
RK3399 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.
Change-Id: Ifff7340bd90b7e9e17c9f500938bee7769785cb9
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch add some required and optional properties for Rockchip
PCIe controller. Also we add a example for how to use it.
Change-Id: I69cfbc6290c97a9a55b50c531da6c4babefd8571
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The CONTROL register offset is different from old SoCs.
For Linux driver, there are not functional changes at all.
Let's call it v2.
Change-Id: I87ab0363fd6a13efe223717ffc6a0ba06ec25d72
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Add compatible string for rk3399 because which timer is a little
different from older SoCs. So rename the file name from
rockchip,rk3288-timer.txt to rockchip,rk-timer.txt.
Clarify rockchip,rk3288-timer supported SoCs.
Change-Id: Ic39196352ebb4740d21c9e5bdf967084192c66d8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The rockchip timer is broadcast timer. Add CLOCK_EVT_FEAT_DYNIRQ
flag and set cpumask to all cpu to save power by avoid unnecessary
wakeups and IPIs.
Change-Id: Ie257972a4a42f6807aed22df695d8b3a4d715045
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
