Actually there is no need to use two loops.
Change-Id: Ieafdc265307e21fc7195f3d80b42483a2d53d413
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
We weren't giving enough time for DMC to change frequencies
when the CPU was running slow.
Change-Id: I84e1a4ad7b5ccddafb0016f3d5d6eef147a58591
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
To protect against races with concurrent CPU online/offline, call
get_online_cpus() before change frequency.
Change-Id: I5b97cd7eff6a1c4828ab30bc165fb2aa8b460bb3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
gpio is not connected by default and we suggest cru mode as the default
shut mode.
Change-Id: I74593092b145e51e5f5b52ab028e650b7fe67f5e
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
update freq of tsadc's working clock as 32768 hz, if not set, tsadc
will work at a default frequence.
Change-Id: I04f3ee230819af1fce44518b5cbee7700c4d67fd
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc hooks. Userspace can make use
of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence would be
used like following:
- mmap dma-buf fd
- for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
want (with the new data being consumed by the GPU or say scanout device)
- munmap once you don't need the buffer any more
BackPort:
upstream kernel change dma-buf api with the commit(831e9da
dma-buf: Remove range-based flush), avoid effect too much to
current kernel, Just compatible dma-buf api to current version.
v2 (Tiago): Fix header file type names (u64 -> __u64)
v3 (Tiago): Add documentation. Use enum dma_buf_sync_flags to the begin/end
dma-buf functions. Check for overflows in start/length.
v4 (Tiago): use 2d regions for sync.
v5 (Tiago): forget about 2d regions (v4); use _IOW in DMA_BUF_IOCTL_SYNC and
remove range information from struct dma_buf_sync.
v6 (Tiago): use __u64 structured padded flags instead enum. Adjust
documentation about the recommendation on using sync ioctls.
v7 (Tiago): Alex' nit on flags definition and being even more wording in the
doc about sync usage.
v9 (Tiago): remove useless is_dma_buf_file check. Fix sync.flags conditionals
and its mask order check. Add <linux/types.h> include in dma-buf.h.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Tiago Vignatti <tiago.vignatti@intel.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455228291-29640-1-git-send-email-tiago.vignatti@intel.com
(cherry picked from commit c11e391da2)
Change-Id: I92916babe7fb0ab3bf3ce9dc966408f2e05fe83d
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
to slove the display shaking, when uboot logo display to kernel show.
Change-Id: I5856581fabd0171be09993878ffb4ef1af0fb204
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
be override as 'sip_fiq_debugger_uart_irq_tf_cb' for optee-os to
jump to fiq_debugger handler. As 'nsec_ctx->und_lr' is not used for
kernel, optee-os uses it to deliver fiq break point's PC.
Change-Id: I5a831638e8228766d03d92674e3e29facdd116f8
Signed-off-by: chenjh <chenjh@rock-chips.com>
support rk805 two clk output,xin32k and rk805-clkout2.
Change-Id: If4f820f53feaf6ab2804f4acd0cce925667b7bc0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If a partner port sends a packet at approximately the same time as we
send a packet, we may end up with the initial packet followed by the
GOOD_CRC reply in our HW FIFO. Don't automatically discard the first
packet in the FIFO. Instead, discard the packet only if it's a GOOD_CRC
packet. And, modify our get_message function to automatically discard
GOOD_CRC in search of a meaningful packet.
In addition, due to interrupt latency, we can't rely on receiving one
interrupt per incoming packet. If our Rx FIFO is non-empty, assume that
it contains at least one packet.
Change-Id: Iaad80a4c55eea3e9e2791d81d7c5d28ce97bd2f5
Signed-off-by: zain wang <wzz@rock-chips.com>
This adds enable CONFIG_KEYBOARD_GPIO to support gpio-keys driver.
Change-Id: Ib2e127a3d017ad69b1bf6c0b0a795d0bce44af0e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The power domain of VCCIO3 is selected from maskrom,
so we don't need to configure it.
Change-Id: I11f87fe6f178943daa5ec9dcc22f4f505fe58163
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch adds nvmem-cells property to opp_table0 node so that
cpufreq driver can get cpu leakage value.
Change-Id: Ic39525de46762dfe867ecb86123be6fa7ccad95c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add a efuse node in the device tree for the rk322x SoC.
Change-Id: I9a771c2065bb222b754f5a37b193edd4abb3f3a7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
this patch is used for rockchip built-in HDMI and audio codec
IC which are wired to the same i2s line(such as rk3368).
so we use a DAI link CPU to multicodecs.
Change-Id: Ibc5fdeb2091836dc28675aacdc099d76e0b7d752
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
It never has the mutex_lock counterpart before goto.
Change-Id: I937e79bc65433cb1c173fe0cb221e7d69586046c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This adds the necessary data for handling efuse on the rk322x.
Change-Id: Iadd37923f5949a03630a936d5a41b955d443b2d8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
