3 Commits

Author	SHA1	Message	Date
Xiaojie Yuan	03d0a073cf	drm/amdgpu: initialize reg base for navi12 ... Set up the register offset map for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-08-02 10:30:39 -05:00
Xiaojie Yuan	a0f6d926f1	drm/amdgpu/soc15: initialize reg base for navi14 (v2) ... Initialize the IP register base offsets for navi14. v2: squash in MP, CLK, THM updates Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-07-18 14:17:58 -05:00
Hawking Zhang	c6b6a42175	drm/amdgpu: add navi10 common ip block (v3) ... This adds the core SOC code for navi asics. v1: add place holder and initial basic function (Ray) v2: add new introduced functions to avoid reference NULL pointer (Hawking) v3L squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>	2019-06-21 18:59:23 -05:00