when other devices bind failed,drm will unbind and re-bind all devices.
if don't cancel the delayed work but flush and destroy workqueue directly,
kernel point is likely to become NULL.
Change-Id: Ib48704186ee298cbd4daac1cdbbac5fb3906b6bb
Signed-off-by: algea.cao <algea.cao@rock-chips.com>
When tested usb device through force device mode method,
we found that usb device failed to connect to usb host
in the following case.
1. Use micro usb 2.0 OTG interface.
2. Plug in otg cable, and the id pin was pulled down
to Ground.
3. User space force usb to enter device mode through
'echo 2 > /sys/bus/platform/drivers/usb20_otg/force_usb_mode'
4. Use usb 2.0 Standard-A to Standard-A cable assembly,
plug into otg cable receptor on one side, and connect
to PC on the other side.
5. PC fail to enumerate our device, because of usb driver
logical issue.
This is because that the dwc_otg_pcd_check_vbus_work()
only enable usb to start connecting if check the bvalid
and iddig is high. But in the above test case, the iddig
is low, so fail to start connection work. In this patch,
we enable usb to connect if iddig is high or usb is in
force device mode.
In addition, fix some coding style to increase the readability.
Change-Id: I08f1a4e6e7e5fb246b1716a20d4572d8b866f238
Signed-off-by: William Wu <william.wu@rock-chips.com>
Rockchip RK3288 has some 64-bit capable DMA and therefore needs
dma_addr_t to be a 64-bit size. One user is the Mali GPU.
Change-Id: I47335415fb101b377c408a2631ce211cb3ae3bd8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Most IP cores on ARM Rockchip platforms can only address 32 bits of
physical memory for DMA. Thus ZONE_DMA should be enabled when LPAE
is activated.
Change-Id: I3fce3e01ba31270f066f49bc14fc2078c70d83ea
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
When build with CONFIG_ARCH_DMA_ADDR_T_64BIT enabled:
drivers/usb/dwc_otg_310/dwc_otg_hcd.c: In function 'assign_and_init_hc':
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1093:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1131:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1161:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1189:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c: In function 'init_non_isoc_dma_desc':
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c:632:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c: In function 'handle_hc_ahberr_intr':
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c:1699:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Change-Id: I4159d1d66ce24c97cc8085ee6e0fc4abde8c7423
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit b001ce5aa46de28c1f52c82d1e3c111e172bd5e4)
(cherry picked from commit 4952c8819aa0f0902ae620bf5de18f7a19f85e17)
VOP pitch register is word align, need align to word.
VOP_WIN0_VIR:
bit[31:16] win0_vir_stride_uv
Number of words of Win0 uv Virtual width
bit[15:0] win0_vir_width
Number of words of Win0 yrgb Virtual width
ARGB888 : win0_vir_width
RGB888 : (win0_vir_width*3/4) + (win0_vir_width%3)
RGB565 : ceil(win0_vir_width/2)
YUV : ceil(win0_vir_width/4)
Change-Id: I89a74fae725e88cf618c5b02c45538419feba28f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
commit accc1ce7d2)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I940fbec4869f1395e66c8e693b838f58aa84a7a1
There are 8 IP blocks pin routes need to be switched, that are
uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
commit cedc964a59)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I48fb4e8aa73930068b9ff6e8e547db267534b04d
There are 9 IP blocks pin routes need to be switched, that are
pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
commit d4970ee076)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9e4fbfb22f37add2ba5941b2b2ae9e55ed2d28b8
On the some rockchip SOCS, some things like rk3399 specific uart2 can use
multiple pins. Somewhere between the pin io-cells and the uart it seems
to have some sort of switch to decide to which pin to actually route the
data.
+-------+ +--------+ /- GPIO4_B0 (pinmux 2)
| uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)
+-------+ +--------+ \- GPIO4_C3 (pinmux 2)
(switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])
The routing switch is determined by one pin of a specific group to be set
to its special pinmux function. If the pinmux setting is wrong for that
pin the ip block won't work correctly anyway.
Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
commit bd35b9bf82)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac
With real-time preemption, regmap functions cannot be used in the
implementation of irq_chip since they use spinlocks which may sleep.
Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler
where we are allowed to sleep.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 88bb94216f)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I94ae59be60c34022fdfdf67cd5b3059d852a5969
We need to avoid calling regmap functions from irq handlers, so the next
commit is going to move the call to rockchip_set_mux() into an
irq_bus_sync_unlock handler. But we can't return an error from there so
we still need to check the settings from rockchip_irq_set_type() and we
will use this new rockchip_verify_mux() function from there.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from git.kernel.org thierry.reding/linux-pwm.git for-next
commit 05709c3e88)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I421f9c2faf835ca821c574602d6b4a66cdde9769
This lock is used from rockchip_irq_set_type() which is part of the
irq_chip implementation and thus must use raw_spinlock_t as documented
in Documentation/gpio/driver.txt.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 70b7aa7a87)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I039ee4067832026f564989a05503e7507d178ee1
regmap_update_bits does its own locking and everything else accessed
here is a local variable so there is no need to lock around it.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit f07bedc37f)
Change-Id: Id15c7ed10f32202c986c951ef328a84be5798af4
Signed-off-by: David Wu <david.wu@rock-chips.com>
To prevent external signal crosstalk, some pins need to
enable input schmitt, like i2c pins, 32k-input pin and so on.
Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit e3b357d7df)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85
if res is error,break;
Change-Id: I4c8a11ae02fef2aa30849a94afcce3af5569bbeb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>
(cherry picked from commit 36bc4c52281bb9f476dc22f8bbd6e35183fa7863)
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
delete node in irqpool list when thread disconnect
Change-Id: I5602e138ab9bce751e24f6dc0a0f7348755be97a
Signed-off-by: zhangyunlong <dalon.zhang@rock-chips.com>
The DP83867 seems to be always in an internal mode on our Board.
This mode can cause connection problems. We disable this mode.
Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved.
If Bit 7 is set, phy is in the internal testing mode.
Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
With FORCE_LINK_GOOD we are not able to get a link.
According to the TRM this bit should be 0 (Normal operation) in default.
Set FORCE_LINK_GOOD to default.
Change-Id: Iaa30bef20fc6f8313c018d18646879f62db49004
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Change-Id: I5d341cac64581cd39ced0703054a70fd1eacc4a6
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Currently dp83867 driver returns error if phy interface type
PHY_INTERFACE_MODE_RGMII_RXID is used to set the rx only internal
delay. Similarly issue happens for PHY_INTERFACE_MODE_RGMII_TXID.
Fix this by checking also the interface type if a particular delay
value is missing in the phy dt bindings. Also update the DT document
accordingly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 34c55cf2fc)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: Ideca1aae2512f0ee2944bc751e47436d8d1746b6
Add documention of ti,min-output-impedance and ti,max-output-impedance
which can be used to correct MAC impedance mismatch using phy extended
registers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit d6081de7e0)
Change-Id: I5e1f90caff7fee13369302a84d1dac370cb75f5e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Change-Id: I416afa8ef29d9a684068fa880f99ca7b720cfd14
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.
Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ac6e058b75)
Change-Id: I1b17b6c88e76230fde3fd1c93c3bb09ee0c2790d
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit fc6d39c395)
Change-Id: Iea19a3e02a5072e5b3ab2b4ee33befd5805100e2
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
programmed as an interrupt output instead of a Powerdown input in
Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
current driver doesn't do this and as result IRQs will not be generated by
DP83867 phy even if they are properly configured in DT.
Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
driver will work properly in interrupt enabled mode.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 5ca7d1ca77)
Change-Id: Ic4fd8e84a2e41f217850230699e00f603ea3f086
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Add support for programmable MAC impedance configuration
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ed838fe937)
Change-Id: I189307e95ccb4f71a245ec69df6f4ab0b32130ec
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
When initializing the PHY control register, the FIFO depth bits are
written without reading the previous register value, i.e. all other
bits are overwritten with zero. This disables automatic MDI-X
configuration, which is enabled by default. Fix initialization by doing
a read/modify/write operation.
Signed-off-by: Stefan Hauser <stefan@shauser.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit b291c41817)
Change-Id: If14021286ff6e8b770f6cfe0f4026e29414e75d8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The address of the device can be determined from the phydev structure,
rather than passing it as a parameter.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 053e7e1692)
Change-Id: Ib0f855bb2f6ad38e37c030343d6ccb1cc8848178
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Device tree properties for a phy device are expected to be in the phy
node. The current code for the DP83867 also tries to look in the
parent node. The devices binding documentation does not mention this,
no current device tree file makes use of this, and it is not behaviour
we want. So remove looking in the parent device.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 7bf9ae016e)
Change-Id: Ia0b9f5fbe15b3c042880b8c8712c1b72f994029e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This patch adds the supporting to the eDP panel sold by
the T-CHIP for the Firefly RK3288. I assign the VOP lite
for the eDP panel and VOP big to HDMI, as the HDMI supports
4K resolution. With a different VOP device, eDP panel
and HDMI could display a different contents.
The InvenSense MPU6050 sensor at the botton of the panel
is also enabled.
The Firefly RK3288 Reload use a different GPIO pin to enable
the power of the eDP panel.
Change-Id: Id78249f001d171ede79fe835d24c40a75ff8a0df
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
ATM dwmac-rk will always set and enable it's internal delay lines.
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.
Tested only with a RK3288 based board.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eaf70ad14c)
Change-Id: Id0152a9f048cbc810b62c252d4105594ed1895df
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.
This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).
(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>
When do reboot test with otg cable plugging in, it may
casue two issues: 1. system hung when access grstctl reg
in dwc_otg_core_reset(); 2. kernel panic when remove the
host channel from the free list in assign_and_init_hc().
This patch adds 1.5~2ms delay afer resume USB2 PHY, the
time for utmi_clk provided from USB2 PHY to stabilize,
and then we can access the usb core registers safely, it
can avoid system hung.
Also, we avoid to call otg20_hcd_connect_detect() if dwc2
is host mode except force host mode during probe, because
we will do the same work in check_id_work() later. This can
fix the issue that init usb core and host twice when boot
with otg cable and usb device, which may cause kernel panic
because of hc list is NULL.
Change-Id: I35aa36762c64b14b580b493d213610379676ab56
Signed-off-by: William Wu <william.wu@rock-chips.com>
If the system rebooted, there might be i2c transfer at the
same time, it will make something unpredictable, because
the i2c host was reseted, but the slave device wasn't, such
as rk808 pmic, so make sure the i2c transfer to be finished
before system shutdown at the reset mode.
Change-Id: I3c09f3acbe86595c295edc191aa38351adb7d5dc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
When build with ARM_LPAE enabled:
arch/arm/mach-rockchip/pm.c: In function 'rk3288_init_pmu_sram':
arch/arm/mach-rockchip/pm.c:85:23: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
Change-Id: I526f13439c3c7edde77a27419d488a8f79081661
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The PD policy would take 5-7s to enter PD disabled state (send
50 times caps, the more bytes of caps cmd, the more time it
takes), So we ough to pick usb notify to PD startup state for
better user experience.
Change-Id: I3b2dc1c5df31296520685ba57e892a30ef3c28aa
Signed-off-by: zain wang <wzz@rock-chips.com>
In the spec:
The tTypeCSendSourceCap is defined from 100ms to 200ms.
The nCapsCount is defined 50.
Change-Id: I09bcdb7a83c353ab099d51228cf8ca13e562d839
Signed-off-by: zain wang <wzz@rock-chips.com>
As the PD spec, we ough to tell policy engine if the cable
support PD, some state would run depend on this value.
Change-Id: Ied725ecb53f71a5e367b1ca91acd7f23372c54a1
Signed-off-by: zain wang <wzz@rock-chips.com>
