there are maximum TMDS clock limit, when the clock is out of range
reducing frequency by set color format to yuv420 and/or set color
depth to 8bit
Change-Id: I8b79de97329561bf0399d05c0264a5c818f844fc
Signed-off-by: xuhuicong <xhc@rock-chips.com>
This is for IC design not reasonable, when enable preoverlay and only
enable win0 for yuv format, the win0 no display area will be considered
as yuv domain black color, this lead to the no display area display
pink color.
Change-Id: I46a860c3753af2aa2a0900db0d48832e1624c948
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
when enable hdr2sdr on rk3328, vop can't support
per-pixel alpha * global alpha, so we must back to gpu,
but gpu can't support hdr2sdr, so gpu output hdr UI(rgbx),
vop will do:
UI(rgbx) -> yuv -> rgb ->hdr2sdr -> overlay -> output.
Change-Id: I69fdfacbf13e755b6fa8b1570c74da027bab52fb
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
when pd power on/off, the qos regs need to save and restore.
Change-Id: I55739fb8f2b452702bdbdc974bd588bbc05848d7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Last_status is used to calculate dmc's power in thermal control.
If last_status is neithor inited nor kept updated, the power model will
get the wrong status and then the wrong power. And dmc gets wrong
cooling state at last.
Meanwhile this issue reports the warning "core: dev_pm_opp_get_voltage
: Invalid parameters"
Change-Id: Ic371796ad94fd6dab376fefbea91adff0068d26b
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
The vpu qos registers need to save and restore when reset.
Change-Id: I649cf4a360842ad1abb06c35a6fd8d3868fbf706
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The rkvdec and vpu qos registers need to save and restore when reset.
Change-Id: If0fbee0aed9227cfd795c5f439cfb8c3b2f0ccaf
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This bit enables the automatic mechanism to stop providing clock in
the clock lane when time allows.
Change-Id: Ia3d85589f54adcf6206ee7ded32624b8e92936af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
use framework internal dynamic power calc function. Do not use
global data, rk_dmcfreq.
Change-Id: I1f46b2471b5d25a9233724fdd61efe63ea13b860
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
There are many isp driver in 4.4 kernel, let's add a dtsi
to help switch between them.
Change-Id: Ida1af575b6c64ffec56ad695933dfdf22cdd72c1
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
We now trap accesses to CNTVCT_EL0 when the counter is broken
enough to require the kernel to mediate the access. But it
turns out that some existing userspace (such as OpenMPI) do
probe for the counter frequency, leading to an UNDEF exception
as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit.
The fix is to handle the exception the same way we do for CNTVCT_EL0.
Fixes: a86bd139f2 ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled")
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 9842119a23)
CVE-2017-13218
Change-Id: I2f163e2511bab6225f319c0a9e732735cbd108a0
Since people seem to make a point in breaking the userspace visible
counter, we have no choice but to trap the access. Add the required
handler.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
(cherry picked from commit 6126ce0588)
CVE-2017-13218
Change-Id: I0705f47c85a78040df38df18f51a4a22500b904d
