crtc is dereferenced from within drm_atomic_get_new_crtc_state, so
check for NULL before initializing new_crtc_state.
Signed-off-by: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Johan writes:
USB-serial updates for v4.15-rc1
Here are the USB-serial updates for 4.15-rc1, including:
- three fixes for longstanding issues in garmin_gps and metro-usb which
could lead to NULL-pointer dereferences and memory leaks
- a workaround for broken f81534 firmware-handling of overruns
- f81534 break support, and
- conversion to timer_setup()
Included are also various clean ups and a new qcserial device id.
All have been in linux-next with no reported issues.
Signed-off-by: Johan Hovold <johan@kernel.org>
This driver converts voltages from a non-linear range in hardware
to a linear range in software and vice versa. During the
conversion, we exclude certain voltages that are invalid to use
because the software interface is more flexible than reality.
For example, the FTSMPS2P5 regulators have a voltage range from
80000uV to 1355000uV that software could support, but we only
want to use the range of 350000uV to 1355000uV. If we don't
account for the hw selectors between 80000uV and 350000uV we'll
pick a hw selector of 0 to mean 350000uV when it really means
80000uV. This can cause us to program voltages into the hardware
that are significantly lower than what we're expecting.
And when we read it back from the hardware we'll have the same
problem, voltages that are in the invalid band will end up being
calculated as some software selector that represents a larger
voltage than what is programmed and the user will be confused.
Fix all this by properly offsetting the software selector and hw
selector when converting from one number space to another.
Fixes: 1b5b196892 ("regulator: qcom_spmi: Only use selector based regulator ops")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
We have 2 bitmaps used to keep track of interrupts dedicated to IPIs in
the MIPS GIC irqchip driver. These bitmaps are only used from the one
compilation unit of that driver, and so can be made static. Do so in
order to avoid polluting the symbol table & global namespace.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The gic_set_type() function included writes to the MIPS GIC polarity,
trigger & dual-trigger registers in each case of a switch statement
determining the IRQs type. This is all well & good when we only have a
single cluster & thus a single GIC whose register we want to update. It
will lead to significant duplication once we have multi-cluster support
& multiple GICs to update.
Refactor this such that we determine values for the polarity, trigger &
dual-trigger registers and then have a single set of register writes
following the switch statement. This will allow us to write the same
values to each GIC in a multi-cluster system in a later patch, rather
than needing to duplicate more register writes in each case.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reserving a number of IPIs based upon the number of VPs reported by the
GIC makes little sense for a few reasons:
- The kernel may have been configured with NR_CPUS less than the number
of VPs in the cluster, in which case using gic_vpes causes us to
reserve more interrupts for IPIs than we will possibly use.
- If a kernel is configured without support for multi-threading & runs
on a system with multi-threading & multiple VPs per core then we'll
similarly reserve more interrupts for IPIs than we will possibly use.
- In systems with multiple clusters the GIC can only provide us with
the number of VPs in its cluster, not across all clusters. In this
case we'll reserve fewer interrupts for IPIs than we need.
Fix these issues by using num_possible_cpus() instead, which in all
cases is actually indicative of how many IPIs we may need.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Rather than configuring EIC mode for all CPUs during boot, configure it
locally on each when they come online. This will become important with
multi-cluster support, since clusters may be powered on & off (for
example via hotplug) and would lose the EIC configuration when powered
off.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We currently walk through the range 0..gic_vpes-1, expecting these
values all to be valid Linux CPU numbers to provide to mips_cm_vp_id(),
and masking all routable local interrupts during boot. This approach has
a few drawbacks:
- In multi-cluster systems we won't have access to all CPU's GIC local
registers when the driver is probed, since clusters (and their GICs)
may be powered down at this point & only brought online later.
- In multi-cluster systems we may power down clusters at runtime, for
example if we offline all CPUs within it via hotplug, and the
cluster's GIC may lose state. We therefore need to reinitialise it
when powering back up, which this approach does not take into
account.
- The range 0..gic_vpes-1 may not all be valid Linux CPU numbers, for
example if we run a kernel configured to support fewer CPUs than the
system it is running on actually has. In this case we'll get garbage
values from mips_cm_vp_id() as we read past the end of the cpu_data
array.
Fix this and simplify the code somewhat by writing an all-bits-set
value to the VP-local reset mask register when a CPU is brought online,
before any local interrupts are configured for it. This removes the need
for us to access all CPUs during driver probe, removing all of the
problems described above.
In the name of simplicity we drop the checks for routability of
interrupts and simply clear the mask bits for all interrupts. Bits for
non-routable local interrupts will have no effect so there's no point
performing extra work to avoid modifying them.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The gic_all_vpes_local_irq_controller chip currently attempts to operate
on all CPUs/VPs in the system when masking or unmasking an interrupt.
This has a few drawbacks:
- In multi-cluster systems we may not always have access to all CPUs in
the system. When all CPUs in a cluster are powered down that
cluster's GIC may also power down, in which case we cannot configure
its state.
- Relatedly, if we power down a cluster after having configured
interrupts for CPUs within it then the cluster's GIC may lose state &
we need to reconfigure it. The current approach doesn't take this
into account.
- It's wasteful if we run Linux on fewer VPs than are present in the
system. For example if we run a uniprocessor kernel on CPU0 of a
system with 16 CPUs then there's no point in us configuring CPUs
1-15.
- The implementation is also lacking in that it expects the range
0..gic_vpes-1 to represent valid Linux CPU numbers which may not
always be the case - for example if we run on a system with more VPs
than the kernel is configured to support.
Fix all of these issues by only configuring the affected interrupts for
CPUs which are online at the time, and recording the configuration in a
new struct gic_all_vpes_chip_data for later use by CPUs being brought
online. We register a CPU hotplug state (reusing
CPUHP_AP_IRQ_GIC_STARTING which the ARM GIC driver uses, and which seems
suitably generic for reuse with the MIPS GIC) and execute
irq_cpu_online() in order to configure the interrupts on the newly
onlined CPU.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The gic_local_irq_domain_map() function has only one callsite in
gic_irq_domain_map(), and the split between the two functions makes it
unclear that they duplicate calculations & checks.
Inline gic_local_irq_domain_map() into gic_irq_domain_map() in order to
clean this up. Doing this makes the following small issues obvious, and
the patch tidies them up:
- Both functions used GIC_HWIRQ_TO_LOCAL() to convert a hwirq number to
a local IRQ number. We now only do this once. Although the compiler
ought to have optimised this away before anyway, the change leaves us
with less duplicate code.
- gic_local_irq_domain_map() had a check for invalid local interrupt
numbers (intr > GIC_LOCAL_INT_FDC). This condition can never occur
because any hwirq higher than those used for local interrupts is a
shared interrupt, which gic_irq_domain_map() already handles
separately. We therefore remove this check.
- The decision of whether to map the interrupt to gic_cpu_pin or
timer_cpu_pin can be handled within the existing switch statement in
gic_irq_domain_map(), shortening the code a little.
The change additionally prepares us nicely for the following patch of
the series which would otherwise need to duplicate the check for whether
a local interrupt should be percpu_devid or just percpu (ie. the switch
statement from gic_irq_domain_map()) in gic_local_irq_domain_map().
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Meson8 uses the same GPIO interrupt controller IP block as the other
Meson SoCs. A total of 134 pins can be spied on, which is the sum of:
- 22 pins on bank GPIOX
- 17 pins on bank GPIOY
- 30 pins on bank GPIODV
- 10 pins on bank GPIOH
- 15 pins on bank GPIOZ
- 7 pins on bank CARD
- 19 pins on bank BOOT
- 14 pins in the AO domain
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
There is a lot of broken firmware out there that don't really
expose the information the kernel requires when it comes with dealing
with GICv2:
(1) Firmware that only describes the first 4kB of GICv2
(2) Firmware that describe 128kB of CPU interface, while
the usable portion of the address space is between
60 and 68kB
So far, we only deal with (2). But we have platforms exhibiting
behaviour (1), resulting in two sub-cases:
(a) The GIC is occupying 8kB, as required by the GICv2 architecture
(b) It is actually spread 128kB, and this is likely to be a version
of (2)
This patch tries to work around both (a) and (b) by poking at
the outside of the described memory region, and try to work out
what is actually there. This is of course unsafe, and should
only be enabled if there is no way to otherwise fix the DT provided
by the firmware (we provide a "irqchip.gicv2_force_probe" option
to that effect).
Note that for the time being, we restrict ourselves to GICv2
implementations provided by ARM, since there I have no knowledge
of an alternative implementations. This could be relaxed if such
an implementation comes to light on a broken platform.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
So far, we require the hypervisor to update the VLPI properties
once the the VLPI mapping has been established. While this
makes it easy for the ITS driver, it creates a window where
an incoming interrupt can be delivered with an unknown set
of properties. Not very nice.
Instead, let's add a "properties" field to the mapping structure,
and use that to configure the VLPI before it actually gets mapped.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The PSCI checker suspend_test_thread() function (ie executed for the
suspend test) requires an on-stack timer to carry out the test it
executes; it sets it up through the setup_timer_on_stack() API.
setup_timer_on_stack() requires its counterpart destroy_timer_on_stack()
to be called when the timer is disposed of but the PSCI checker code is
currently missing that call, leaving the timer object in an incosistent
state when the PSCI checker stops the thread executing the suspend
test.
Add the missing destroy_timer_on_stack() call to fix the omission.
Fixes: ea8b1c4a60 ("drivers: psci: PSCI checker module")
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reported-by: Kees Cook <keescook@chromium.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "Mediatek: soc driver updates for v4.15" from Matthias Brugger:
- add 32 bit read/write support to pwrap
- add mt7622 support to pwrap
- test build all mediatek soc drivers
- fix compiler issues
- clean up Kconfig description
* tag 'v4.14-next-soc' of https://github.com/mbgg/linux-mediatek:
soc: mediatek: pwrap: fix fatal compiler error
soc: mediatek: pwrap: fix compiler errors
arm64: mediatek: cleanup message for platform selection
soc: Allow test-building of MediaTek drivers
soc: mediatek: place Kconfig for all SoC drivers under menu
soc: mediatek: pwrap: add support for MT7622 SoC
soc: mediatek: pwrap: add common way for setup CS timing extenstion
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode
dt-bindings: arm: mediatek: add MT7622 string to the PMIC wrapper doc
ARM: mediatek: Cocci spatch "of_table"
soc: mediatek: pwrap: fixup warnings from coding style
Pull "soc for 4.15" from Alexandre Belloni:
- add SoC ids for the sama5d2 SiPs
- Improve the AT91 maintainers entry
* tag 'at91-ab-4.15-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
MAINTAINERS: Add SoC drivers to AT91 entry
drivers: soc: atmel: Add basic support for new sama5d2 SiPs
Pull "Amlogic drivers for v4.15" from Kevin Hilman:
- add SoC info driver for 32-bit Amlogic SoCs
* tag 'amlogic-drivers' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
soc: amlogic: Add Meson6/Meson8/Meson8b/Meson8m2 SoC Information driver
Pull "Qualcomm ARM Based Driver Updates for v4.15 Part 2" from Andy Gross:
* Add Qualcomm Remote Filesystem Memory driver
* Add OF linkage for RMTFS
* tag 'qcom-drivers-for-4.15-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/agross/linux:
soc: qcom: Remote filesystem memory driver
dt-binding: soc: qcom: Add binding for rmtfs memory
of: reserved_mem: Accessor for acquiring reserved_mem
of/platform: Generalize /reserved-memory handling
Pull "Keystone SOC for 4.15" from Santosh Shilimkar
* tag 'keystone_soc_drivers_4.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ti_sci: Use %pS printk format for direct addresses
Pull "Broadcom drivers changes for 4.15 (part 2)" from Florian Fainelli:
This pull request contains Broadcom ARM/ARM64/MIPS SoCs changes for 4.15
(second part), please pull the following:
- Markus updates the Broadcom STB DPFE driver to avoid loading the firmware when
unnecessary to accomodate for specific platform restrictions
- Florian adds support for the Broadcom Hurricane 2 SoC iProc PLL clock needed
to get the proper CPU clock frequency
* tag 'arm-soc/for-4.15/drivers-part2' of http://github.com/Broadcom/stblinux:
clk: bcm: Add Broadcom Hurricane 2 clock support
memory: brcmstb: dpfe: skip downloading firmware when possible
memory: brcmstb: dpfe: introduce is_dcpu_enabled()
Pull "thermal: tegra: Changes for v4.15-rc1" from Thierry Reding:
This contains the Tegra186 BPMP thermal driver. It is used to monitor
and access several thermal sensors found in the SoC.
* tag 'tegra-for-4.15-thermal' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
thermal: Add Tegra BPMP thermal sensor driver
dt-bindings: Add bindings for nvidia,tegra186-bpmp-thermal
dt-bindings: clock: tegra: Add sor1_out clock
Pull "soc/tegra: Changes for v4.15-rc1" from Thierry Reding:
Contains a fix to the generic power domain driver to properly report
errors propagated from BPMP.
* tag 'tegra-for-4.15-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: bpmp: Check BPMP response return code
Pull "firmware: tegra: Changes for v4.15-rc1" from Thierry Reding:
This contains a couple of (non-critical) fixes and improvements for the
BPMP driver as well as support for debugfs.
* tag 'tegra-for-4.15-firmware' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
firmware: tegra: Add BPMP debugfs support
firmware: tegra: Add stubs when BPMP not enabled
firmware: tegra: Expose tegra_bpmp_mrq_return()
firmware: tegra: Propagate error code to caller
Like many storage drivers, skd uses an unsigned 32-bit number for
interchanging the current time with the firmware. This will overflow in
y2106 and is otherwise safe.
However, the get_seconds() function is generally considered deprecated
since the behavior is different between 32-bit and 64-bit architectures,
and using it may indicate a bigger problem.
To annotate that we've thought about this, let's add a comment here
and migrate to the ktime_get_real_seconds() function that consistently
returns a 64-bit number.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
After the cdrom cleanup, I get randconfig warnings for some configurations:
warning: (BLK_DEV_IDECD && BLK_DEV_SR) selects CDROM which has unmet direct dependencies (BLK_DEV)
This adds an explicit BLK_DEV dependency for both drivers. The other
drivers that select 'CDROM' already have this and don't need a change.
Fixes: 2a750166a5 ("block: Rework drivers/cdrom/Makefile")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
The recent CTO timer introduced in commit 03de19212e ("mmc: dw_mmc:
introduce timer for broken command transfer over scheme") was causing
observable problems due to race conditions. Previous patches have
fixed those race conditions.
It can be observed that these same race conditions ought to be
theoretically possible with the DTO timer too though they are
massively less likely to happen because the data timeout is always set
to 0xffffff right now. That means even at a 200 MHz card clock we
were arming the DTO timer for 94 ms:
>>> (0xffffff * 1000. / 200000000) + 10
93.886075
We always also were setting the DTO timer _after_ starting the
transfer, unlike how the old code was seting the CTO timer.
In any case, even though the DTO timer is much less likely to have
races, it still makes sense to add code to handle it _just in case_.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Add a jump target so that a specific string copy operation is stored
only once at the end of this function implementation.
Replace two calls of the function "strncpy" by goto statements.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Add a jump target so that a bit of exception handling can be better
reused at the end of this function.
* Adjust condition checks.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Some Intel host controllers use an ACPI device-specific method to ensure
correct voltage switching. Fix voltage switch for those, by adding a call
to the DSM.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Let devices define their own private data to facilitate device-specific
operations. The size of the private structure is specified in the
sdhci_acpi_slot structure, then sdhci_acpi_probe() will allocate extra
space for it, and sdhci_acpi_priv() can be used to get a reference to it.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
some platform(eg.mt2701) does not support "stop clk fix", in
this case, need set correct latch-ck to avoid crc error caused
by stop clock block-internally.
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
source clock need an independent cg to control, when doing clk mode
switch, need gate source clock to avoid hw issue(multi-bit sync hw hang)
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
bit7 of PATCH_BIT1 has different meaning in new design, to
compatible with previous platform, clear this bit in new
platform.
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
the origin design of hs400_tune_response is for mt8173 because of
mt8173 has a special design. for doing that, we add a new member
"compatible", by now it's only for mt8173.
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
