The PMU Cortex M0 on rk3399 is intended to be used for things like
DDRFreq transitions, suspend/resume, and other things that are the
purview of ARM Trusted Firmware and not the kernel. As such, the
kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to
these clocks.
Without this change, the following was observed on a Chromebook with a
rk3399 (using not-yet-upstream ARM Trusted Firmware code and
not-yet-upstream kernel code based on kernel-4.4):
1. We init the clock framework.
2. We start up "DDRFreq", which causes ATF to occasionally fire up the
M0 for transitions. Each time ATF fires up the M0 it will turn on
these clocks and each time it is done it will turn them off.
3. We finally get to the the part of the kernel that calls
clk_disable_unused() and we disables the clocks.
You can see the race above. Basically everything is fine as long as
ARM Trusted Firmware isn't starting up the M0 at exactly the same time
that the kernel is disabling unused clocks. ...but if the race
happens then we go boom.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 60aadea57e)
Change-Id: I2a78c74edc9bc5d5b4f26224ebdb34eb83afb022
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4ee3fd4abe)
Change-Id: I118c877882d694b358697470225d8d94cb1271b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a bit of headphone pop during power on, we
need to increase delay time (200us per loop step).
It looks fine that it may take 200us*128=25.6ms here.
Change-Id: Idbc5b235fd55c26cd71f4693cce98fccce60368f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rk3326 and other platform power management implementation
Change-Id: I34b9c773cfee1e684e833cdbcf687ac54cd8d88a
Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Add usic node for rk3399 USB 2.0 EHCI controller
with usic phy.
Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf
Signed-off-by: William Wu <william.wu@rock-chips.com>
Some EHCI controllers use usic phy (e.g rk3399/rk3288),
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Support this feature in device tree when using the ehci
platform driver by adding a new property for it.
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
During dwc3 resume, it shoudn't reset otg controller logic
if device is connecting with the otg port, because it will
cause device to be reenumerated. More seriously, it may
cause the otg_work to enter disconnect process and power
down usb3 controller power domain, at the same time, if
the xHCI driver is accessing the controller asynchronously,
it will cause system hang.
Change-Id: Id546277bd4082b7baeff830788643a800330ae8e
Signed-off-by: William Wu <william.wu@rock-chips.com>
When do core init, only reset the core for device mode.
Becasue in host mode, xHCI driver will reset the core
and its host block via usbcmd.hcrst. If we do core reset
in dwc3_core_init() for host mode, it will reset both
the dwc3 core registers and xHCI registers, and cause
device to be reenumerated when usb suspend/resume.
Change-Id: If723ce8a771975e9757d28cb2c114d6269581677
Signed-off-by: William Wu <william.wu@rock-chips.com>
By default, only using lrck_tx for PCM by hardware,
therefore, we need to use I2S_CKR_TRCM_TXONLY.
Change-Id: I6c4077e7e7e65b8a3a21416fd61d5900b3b72f42
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch using PCM rising late1 and slave mode for
Bluetooth HFP.
Change-Id: I4a0188134d7d0ef0690c6c7c9f94fc8ec50c1671
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If there is only one lrck (tx or rx) by hardware, we need to
use 'rockchip,clk-trcm' specify which lrck can be used.
Change-Id: I3bf8d87a6bc8c45e183040012d87d8be21a4c133
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Python 3 requires parentheses in call to 'print', meanwhile
the 'line' could be bytes-like, let's decoding to str as utf-8.
This makes the gcc-wrapper.py compatible with both 2.7 and 3.
For example, a bytes-like string as below,
b'kernel/reboot.c:47:13: error: function declaration isn\xe2\x80\x99t a
prototype [-Werror=strict-prototypes]\n'
b' static void no_use()\n'
b' ^~~~~~\n'
After decoding, it looks like,
kernel/reboot.c:47:13: error: function declaration isn’t a prototype
[-Werror=strict-prototypes]
static void no_use()
^~~~~~
Change-Id: Icacdbe2ca7b7ab674ab90e54b79d3176e0061ac6
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
The reserved root blocks is not enough for booting Android due to
the limit of 0.2% if the fs size too small. so we add a new mini-
mum limit is 128MB.
Change-Id: I5af3b182001d27e4d18b4090c5270bbb2ac6253b
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Here should use the mapped grp as a reference, not idx.
Change-Id: Ia40dafc11f4f5f077f764f49985bb8d3ec800c28
Reported-by: Lin Jianhua <linjh@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
After commit 7e4da3fcf7 ("usb: gadget: composite:
Test get_alt() presence instead of set_alt()") f_uac1
function became broken because it doesn't have
get_alt() callback implementation and composite
framework never set altsetting 1 for audiostreaming
interface. On host site it looks like:
[424339.017711] 21:1:1: usb_set_interface failed (-32)
Since host can't set altsetting 1, it can't start
playing audio.
In order to fix it implemented get_alt along with
minor improvements (error conditions checking)
similar to what existing f_uac2 has.
Change-Id: I41d59c69e3b300b164e6267c48c1367e8d38b098
Cc: Krzysztof Opasiak <k.opasiak@samsung.com>
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 1fc4926d92)
To avoid "too much work for irq" issue, cherry pick the the patch.
It reads the RBR to clear the time out interrupt, but sometime the
rx fifo may be not empty while cpu reads the RBR. Which would cause
the data lost.
patch for "too much work":06451e93ab59e5b1843c29cbb468a274f4919563
By the way, current patch can't get rid of the risk entirely, so I
try a lot to solve it. Unfortunately, I only got the phenomenon that
lower pclk can reduce the probability. And I check the dw data sheet,
it has pclk and sclk, so there is synchronization problem. But it
only requires (slck < 4*pclk).
Change-Id: I01a36c689b43310294c45294abcf4982f5ddf2af
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
This patch tried to rename arch/arm64/boot/dts/rockchip/
{rk3326-evb-linux-lp3-v10.dts => rk3326-evb-lp3-v10-linux.dts},
and correct the right things as below.
* define the rootfs type as the squashfs.
* fixes some typo
* copyright to 2018
Change-Id: I5fed2e472c979d5209222ad51281b01148379efb
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
If edid can't be got when hdmi plug in, hdmi color depth mask and format
won't be updated. The color list in the setting are those of the previous
TV. This commit fix the error.
Change-Id: Iffe3164af1f1ad32002c26b5bbac14f2ff417c96
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If edid can't be got when hdmi plug in, hdmi color depth mask and format
won't be updated. The color list in the setting are those of the previous
TV. This commit fix the error.
Change-Id: I5ed4be5efa2a69be0b58489f58a3af5de9912292
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
