After comparing the test results with RIE enabled and disabled,enable
RIE may cause PCIe dma interrupt work unnormal.
More works need to dig it out
Change-Id: Ia25022332de92cf21287df155cd514a160d140bc
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Add wakeup-source to uart dts node to enable uart
wake up system when it receives data.
Change-Id: If4e82a4d3dbaca708209553dc3693089864c782f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
If we use the channels which are less than en_always_grps_num,
we don't need to set the flag to skip_grps which are not used.
And, the skip grps need to refer to mapped_grps
For example, if:
rockchip,en-always-grps = <1 2 3>;
rockchip,adc-grps-route = <2 1 3 0>;
The DUT startup and capture 2ch at first, we just open grp2
and set skip_grp[2]=1.
Then, if we capture 4ch, we just skip grp2, open grp1, and
set skip_grp[1]=1.
To capture 6ch: we skip grp2/grp1, open grp3 and set skip_grp[3]=1.
To capture 8ch: we skip grp2/grp1/grp3 and open grp0.
Change-Id: I88c0b220ce0e714abafda1be3c895ad1c5c9ddca
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The Seagate Expansion Portable Drive HDD (idVendor=0bc2, idProduct=2321)
is reported to fail to work on rockchip platforms with the following error
message when do read/write operation by dd command:
xhci-hcd xhci-hcd.11.auto: Ring expansion failed
According to tkaiser's suggestion[1], we can try to increase the kernel's
coherent-pool memory size to fix this issue. The kernel coherent-pool memory
size was limited at 256KB by default. When set the DEFAULT_DMA_COHERENT_POOL_SIZE
to 1MB, the error "Ring expansion failed" can be fixed, but it still not
work with the other error message:
xhci-hcd xhci-hcd.12.auto: ERROR Unknown event condition 34 for slot 1 ep 3 , HC probably busted
sd 0:0:0:0: [sda] tag#16 uas_eh_abort_handler 0 uas-tag 17 inflight: CMD OUT
...
scsi host0: uas_eh_bus_reset_handler start
xhci-hcd xhci-hcd.12.auto: ERROR Transfer event for disabled endpoint slot 1 ep 6 or incorrect stream ring
Falling back to USB mass storage can solve this problem, so ignore UAS
function of this HDD.
[1] https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
Change-Id: I0d817cc3aaea548c2060b323c3077c6cbbd3bb6e
Signed-off-by: William Wu <william.wu@rock-chips.com>
This adds the necessary data for handling efuse on the rk1808.
Change-Id: I78b66db1fdc22430ab93b07ad3c7cea3355a7f6e
Signed-off-by: Liang Chen <cl@rock-chips.com>
stop stream just close data output, csi phy state maybe not ok
for next start stream. so reset and config csi during stop stream.
Change-Id: Ic2eea6058249c294a5a4c036c87bf0b655986025
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
reduce 1296x972 regs.
reg list write change to continue instead of one by one.
TODO: to i2c write faster, config i2c to 400k.
clock-frequency = <400000>; to i2c node.
Change-Id: I4294cb9ba37bd1e2550a122ff45420a66911ebd9
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
current frame end to stop mp or sp, and next
frame to close, will take a frame time.
change to stop immediately and current frame end
to close.
Change-Id: I7d1b8fa23d13de1ee637d076ee0e75cbcb62e7e6
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
There is no dc detect pin in the hardware design,
dc charge only detect by rk809 vdc pin.
Change-Id: I17075bcf23b966e9d2e0a8a5daeedf26e253818d
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
When playing NLPCM audio, such as AC3, HDMI is pluged in, it's
better to reset audio fifo and sync audio clock by reselect
audio input interface. Or sink may not recognize NLPCM format.
Change-Id: I9112bc9aa1f57041e15b5be563ecb96c44644807
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
enable rk808 related config, so we can adjust voltage on rk1808x4
board.
Change-Id: I28ba4da20176a4e7f10afeb4e7c1389f4aa920ed
Signed-off-by: Lin Huang <hl@rock-chips.com>
This issue is caused by set wake_host_gpio to out put,
so cancel set wake_host_gpio to out put
Change-Id: If776c1a9f54914cf0da728925fb8c8bbb5886155
Signed-off-by: Longjian Lin <llj@rock-chips.com>
Now we have a way retraining the link in case link broken
during PCIe transfer by uDMA
Change-Id: Ica4a2dfff432515bd8d32e79b8fb9504de56e82d
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Debugfs may not support on some platforms. So remove
the debugfs and add sysfs interface. This patch also
change the name "rk_usb_force_mode" to "dwc3_mode".
Change-Id: I461919a02b1ee126c494f43f74af5295bb20c0a4
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fix some coding style issues reported by checkpatch.pl.
Change-Id: I6a0163fb849203e722dc0e462ddaf3f96cd080a7
Signed-off-by: William Wu <william.wu@rock-chips.com>
As policy->cur may be changed by thermal and cpufreq_suspend, the setspeed
may be changed after resume.
Change-Id: I6d4e0672ff39127c522f305719afd52806c31f48
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
if miss this commit will appear hdmi display abnormal at
some TV.
Change-Id: I09833db307dae9622319940ac4f773836db1de81
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The bus format is therefore retrieved from the connected panel
information.
Change-Id: Ie8489f75f828f25d6bdd59e8d1efb7959a3a6a28
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
On LVDS buses, usually each sample is transferred serialized in seven
time slots per pixel clock, on three (18-bit) or four (24-bit) differential
data pairs at the same time. The remaining bits are used for control signals
as defined by SPWG/PSWG/VESA or JEIDA standards. The 24-bit RGB format
serialized in seven time slots on four lanes using JEIDA defined bit mapping
will be named MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, for example.
LVDS RGB formats
-----------------------------------------------------------------------
Identifier Code Data organization
Timeslot Lane 3 2 1 0
MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 0 d b1 g0
1 d b0 r5
2 d g5 r4
3 b5 g4 r3
4 b4 g3 r2
5 b3 g2 r1
6 b2 g1 r0
MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 0 d d b1 g0
1 b7 d b0 r5
2 b6 d g5 r4
3 g7 b5 g4 r3
4 g6 b4 g3 r2
5 r7 b3 g2 r1
6 r6 b2 g1 r0
MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 0 d d b3 g2
1 b1 d b2 r7
2 b0 d g7 r6
3 g1 b7 g6 r5
4 g0 b6 g5 r4
5 r1 b5 g4 r3
6 r0 b4 g3 r2
Change-Id: I7ca6442a761ac6ff29eb8b23d57647bf14d734ba
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
