The old mode uses soft timer to update received data,
which costs much cpu resource, even though there is no
data. The new mode is based on uart time out, it updates
data only when transfer completes.
Change-Id: Id12e351ff00015e4bfb36f416731ce4af5330001
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The UART CPR may be 0 of some rockchip soc,
but it supports fifo and AFC, fifo entry is 32 default.
Change-Id: I44f420c556f703c2848c38dc8449546274ef887d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Px30 afbdc made some improvements base on rk3399:
1. support virth width;
2. support buffer xoffset and yoffset;
Change-Id: I6d5b8bc0a66e468882998c9940da21812896b5c4
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
PX30 have two vop(vopb and vopl), the vopb have win0, win1 and win2,
the vopl have win1.
win0: support yuv and scale;
win1: support rgbx and afbdc format(vopb only);
win2: support rgbx and four region;
Change-Id: Ibb0ec88bb6c0a5e031d21432a86734fc9267fd1d
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Add an intermediate opp so that rkvdec clock rate can be set to
an intermediate rate when temperature is above the trip point.
Change-Id: Ia94910185c708a501072c5da8aaebfcb206ad76b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Some chips need adjust opp level by different chip-process, add
common functions to select opp level from device-tree, so modules
can select opp level easy.
Change-Id: Ifbd5f720e6a52a68f13697bbb37ac01ff4a87e3e
Signed-off-by: Liang Chen <cl@rock-chips.com>
Solve the cvbs color err after switch from hdmi by
setting cvbs tv state.
Change-Id: Iaf50c2dbbf954fc8437395b88c41846ca47631f3
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Set cvbs color space to V4L2_COLORSPACE_SMPTE170M
to prevent display err.
Change-Id: I12cb71938e9c423397d64f68a46a257e7e0af5c4
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
On some sink, e.g. Philips 24PFL3545/T3, Y data which is transmitted
in the D1 channel was recognized error, and picture will show noise.
It's fixed after enable the 150ohm differential resistance.
Change-Id: Ie1197dc78260bf7931786ebbccf98e9599b66ccd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If put cec_notifier_set_phys_addr in rxsense setup, hdmi->mutex may
become deadlock. Because cec_notifier_set_phys_addr will call
dw_hdmi_cec_enable which cause hdmi->mutex become deadlock.
Change-Id: I4fed641c9e9d7674451402a973196ef0efeb198f
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
In rockchip_clk_register_ddrclk,
ifdef CONFIG_ARM
if (!psci_smp_available())
return NULL;
endif
Add "__init" for rockchip_clk_register_ddrclk() to match with
psci_smp_available().
Change-Id: Ib6849e359921c3a937bf8dc4f6547aed353f1071
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Support the "cec" optional clock. The documentation already mentions "cec"
optional clock and it is used by several boards, but currently the driver
doesn't enable it, thus preventing cec from working on those boards.
And even worse: a /dev/cecX device will appear for those boards, but it
won't be functioning without configuring this clock.
Changes:
v4:
- Change commit message to stress the importance of this patch
v3:
- Drop useless braces
v2:
- Separate ENOENT errors from others
- Propagate other errors (especially -EPROBE_DEFER)
Signed-off-by: Pierre-Hugues Husson <phh@phh.me>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20171125201844.11353-1-phh@phh.me
(cherry picked from commit ebe32c3e28)
Change-Id: I084e254f7ee1b2c537d3f18897d64578e8bfd482
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This change adds USB-PHY output clock reference for EHCI and OHCI.
Change-Id: I39e91fed99756a86c83fe9332587c6630a5e5853
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We found that the system was blocked in EHCI when perform suspend or
reboot on RK3288 platform, the root cause is that EHCI (auto) suspend
causes the corresponding usb-phy into suspend mode which would power
down the inner PLL blocks in usb-phy if the COMMONONN is set to 1'b1.
The PLL output clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
and so on, these clocks are not only supplied for EHCI and OHCI, but also
supplied for GPU and other external modules, so setting COMMONONN to 1'b0
to keep the inner PLL blocks in usb-phy always powered.
Change-Id: Ifb7f3d233cf72155aa54d20b15a62b683944a526
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.
So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
(cherry picked from commit 219a5859c8)
Conflicts:
drivers/clk/rockchip/clk-rk3188.c
Change-Id: Ib7dce56943e2642833285fb89dd1aeb9328f84a7
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
For PMIC that power off supplies by write register via i2c bus,
it's better to do power off at syscore shutdown.
Because when run to kernel's "pm_power_off" call, i2c may has
been stopped or PMIC may not be able to get i2c transfer while
there are too many devices are competiting.
This patch effects on PMIC: RK808/RK818/RK816, not including RK805
which power off system by pull up pmic sleep pin in ATF.
Change-Id: I116f79dc91f6f10c6d8070a9168eea44954bf01f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
When userspace closes a handle, we remove it from the file->object_idr
and then tell the driver to drop its references to that file/handle.
However, as the file/handle is already available again for reuse, it may
be reallocated back to userspace and active on a new object before the
driver has had a chance to drop the old file/handle references.
Whilst calling back into the driver, we have to drop the
file->table_lock spinlock and so to prevent reusing the closed handle we
mark that handle as stale in the idr, perform the callback and then
remove the handle. We set the stale handle to point to the NULL object,
then any idr_find() whilst the driver is removing the handle will return
NULL, just as if the handle is already removed from idr.
Note: This will be used to have a direct handle -> vma lookup table,
instead of first a handle -> obj lookup, and then an (obj, vm) -> vma
lookup.
v2: Use NULL rather than an ERR_PTR to avoid having to adjust callers.
idr_alloc() tracks existing handles using an internal bitmap, so we are
free to use the NULL object as our stale identifier.
v3: Needed to update the return value check after changing from using
the stale error pointer to NULL.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Thierry Reding <treding@nvidia.com>
[danvet: Add note about the use-case.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1460721308-32405-1-git-send-email-chris@chris-wilson.co.uk
(cherry picked from commit f6cd7daecf)
Change-Id: Icfa68bd1916c6a3f3b13a33b648bad5006ee2f80
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This has been done in drivers/cpufreq/rockchip-cpufreq.c
Change-Id: Ie3142f1db99560e596706871a67af6e2e06f5153
Signed-off-by: Liang Chen <cl@rock-chips.com>
If the register isn't define at rockchip_vop_reg.c, the default value
of reg.major is 0, this will lead to judge error. so we add reg.mask
conditions because if it's defined register, the reg.mask can't be 0.
Change-Id: I753b92476fda15a64f94e4a8a47894c5ac3a1a7f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Update clock debugfs to support the below functionalities.
- Allow enable/disable a clock.
- Allow set_rate on a clock.
- Display available parent of a clock.
- Allow set_parent on a clock.
- Display the list of enabled_clocks along with prepare_count,
enable_count and rate.
Change-Id: Ib67b3a3409c9e7d8adb710bb524f54f543abf712
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
For next Soc VOP only vopb win1 support AFBDC, so we need
add afbdc feature for every win.
Change-Id: Icbe5e26189d2147a6b81f2f75d0b855b2c35fd26
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This adds the necessary data for handling dmcfreq on the rk3328
Change-Id: If4cff5cc372f80b6776a7272a1bff54abef2cf33
Signed-off-by: CanYang He <hcy@rock-chips.com>
This adds the necessary data for handling dfi on the rk3328.
Change-Id: Id870f78dad3ddd6cb5771674a4e8905322f9e8ef
Signed-off-by: CanYang He <hcy@rock-chips.com>
after modify, rockchip_dfi_ops can apply to other platform use such
version ddr monitor. regardless of channel count, only one channel
of rk3288,rk3399,rk3328 can work. and regardless of monitor clk,
some platform like rk3328 monitor clk is always on.
Change-Id: Ia1c02a89116546ded385c5a6a3e36d020d66b7f3
Signed-off-by: CanYang He <hcy@rock-chips.com>
After commit 169c390240 ("drivers: rk_nand: support global partition table"),
the partition "rknand_rknand" will not create for firmware upgrade.
This commit will fix this issue and can be compatible with GPT.
Change-Id: I919c1f37358a84bf9fd53830235d0868b6352b80
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
