The "powernv" platform of the powerpc architecture needs to assign PCI
resources using a specific algorithm to fit some HW constraints of
the IBM "IODA" architecture (related to the ability to create error
handling domains that encompass specific segments of MMIO space).
For doing so, it wants to call pci_setup_bridge() from architecture
specific resource management in order to configure bridges after all
resources have been assigned. So make it non-static.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
As with any other such change, the goal is to prevent inadvertent
writes to these structures (assuming DEBUG_RODATA is enabled), and to
separate data (possibly frequently) written to from such never getting
modified.
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Using legacy interrupts and TLPs > 256 bytes on the SFC4000 (all
revisions) may cause interrupt messages to be replayed. In some
systems this results in a non-recoverable MCE. Early boards using the
SFC4000 set the maximum payload size supported (MPSS) to 1024 bytes
and we should override that.
There are probably other devices with similar issues, so give this
quirk a generic name.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
On some build configurations PER_CLEAR_ON_SETID symbol was not
found when compiling smack_lsm.c. This patch fixes the issue by
explicitly doing #include <linux/personality.h>.
Signed-off-by: Jarkko Sakkinen <jarkko.j.sakkinen@gmail.com>
Signed-off-by: Casey Schaufler <cschaufler@cschaufler-intel.(none)>
The trace_pipe_raw handler holds a cached page from the time the file
is opened to the time it is closed. The cached page is used to handle
the case of the user space buffer being smaller than what was read from
the ring buffer. The left over buffer is held in the cache so that the
next read will continue where the data left off.
After EOF is returned (no more data in the buffer), the index of
the cached page is set to zero. If a user app reads the page again
after EOF, the check in the buffer will see that the cached page
is less than page size and will return the cached page again. This
will cause reading the trace_pipe_raw again after EOF to return
duplicate data, making the output look like the time went backwards
but instead data is just repeated.
The fix is to not reset the index right after all data is read
from the cache, but to reset it after all data is read and more
data exists in the ring buffer.
Cc: stable <stable@kernel.org>
Reported-by: Jeremy Eder <jeder@redhat.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
BUG: sleeping function called from invalid context at /local/scratch/dariof/linux/kernel/mutex.c:271
in_atomic(): 1, irqs_disabled(): 0, pid: 3256, name: qemu-dm
1 lock held by qemu-dm/3256:
#0: (&(&priv->lock)->rlock){......}, at: [<ffffffff813223da>] gntdev_ioctl+0x2bd/0x4d5
Pid: 3256, comm: qemu-dm Tainted: G W 3.1.0-rc8+ #5
Call Trace:
[<ffffffff81054594>] __might_sleep+0x131/0x135
[<ffffffff816bd64f>] mutex_lock_nested+0x25/0x45
[<ffffffff8131c7c8>] free_xenballooned_pages+0x20/0xb1
[<ffffffff8132194d>] gntdev_put_map+0xa8/0xdb
[<ffffffff816be546>] ? _raw_spin_lock+0x71/0x7a
[<ffffffff813223da>] ? gntdev_ioctl+0x2bd/0x4d5
[<ffffffff8132243c>] gntdev_ioctl+0x31f/0x4d5
[<ffffffff81007d62>] ? check_events+0x12/0x20
[<ffffffff811433bc>] do_vfs_ioctl+0x488/0x4d7
[<ffffffff81007d4f>] ? xen_restore_fl_direct_reloc+0x4/0x4
[<ffffffff8109168b>] ? lock_release+0x21c/0x229
[<ffffffff81135cdd>] ? rcu_read_unlock+0x21/0x32
[<ffffffff81143452>] sys_ioctl+0x47/0x6a
[<ffffffff816bfd82>] system_call_fastpath+0x16/0x1b
gntdev_put_map tries to acquire a mutex when freeing pages back to the
xenballoon pool, so it cannot be called with a spinlock held. In
gntdev_release, the spinlock is not needed as we are freeing the
structure later; in the ioctl, only the list manipulation needs to be
under the lock.
Reported-and-Tested-By: Dario Faggioli <dario.faggioli@citrix.com>
Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
The xenstore daemon does not have to run in the xen initial domain;
however, Linux currently uses xen_initial_domain to test if a loopback
event channel should be used instead of the event channel provided in
Xen's start_info structure. Instead, if the event channel passed in the
start_info structure is not valid, assume that this domain will run
xenstored locally and set up the event channel.
Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
Reviewed-by: Ian Campbell <Ian.Campbell@citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
The xenbus event channel established in xenbus_init is intended to be a
loopback channel, but the remote domain was hardcoded to 0; this will
cause the channel to be unusable when xenstore is not being run in
domain 0.
Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
Reviewed-by: Ian Campbell <Ian.Campbell@citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.
I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
As far as I can tell the only reason microblaze has
__ARCH_WANT_INTERRUPTS_ON_CTXSW is because it initializes new task state
with interrupts enabled so that on switch_to() interrupts get enabled.
So change copy_thread() to clear MSR_IE instead of set it, this will
ensure switch_to() will always keep IRQs disabled.
The scheduler will disable IRQs when taking rq->lock in schedule() and
enable IRQs in finish_lock_switch() after its done its magic.
This leaves ARM the only __ARCH_WANT_INTERRUPTS_ON_CTXSW user.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Add missing __ucmpdi2 helper function.
Error log:
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'
Based on MIPS code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
It fixes the signal nr raised for divizion by zero from
SIGILL to SIGFPE, in accordance to POSIX and other archs.
This came up due to a failed test in the GCC testsuite.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Switch arch code to 189, the registered code in the upstream
version of binutils. Continue to accept the experimental 0xbaab.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Added support gor dma_direct_sync_single_for_*() and dma_direct_sync_sg_for_*()
Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
__dma_sync_page() was replaced by __dma_sync(), and parameters of calls to
the new function were adjusted to match __dma_sync()'s format.
Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
There is the problem with bit OR (|) because for
some combination is addr | size | addr+size equal
to seq.
For standard kernel setting (kernel starts at 0xC0000000)
is seq for user space 0xBFFFFFFF and everything below
this limit is fine.
But even address 0xBFFFFFFF is fine because it
is below kernel space.
Signed-off-by: Andrew Fedonczuk <andrew.fedonczuk@ericsson.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Top bit is used as garbage and it must be clear
explicitly.
It is causing the problem with soft lookup code
because it checks delays which are long when
top bit is setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Add support for DiskOnChip G3 chips. The support is quite
limited yet :
- no flash writes/erases are implemented
- ECC fixes are not implemented
- powerdown is not implemented
- IPL handling is not yet done
On the brighter side, the chip reading does work.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Add support for the msi-address-64 property of a PCI node. This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).
In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly. These fields are replace with a single field, msiir_offset,
to reflect the new meaning.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Since commit af337f3e63
"ARM: S3C2443: Move parts of the clock code to common clock file",
the init_clocks array is moved to arch/arm/plat-s3c24xx/s3c2443-clock.c.
Now we call s3c_register_clocks for init_clocks in s3c2443_common_init_clocks.
Thus we can remove the empty init_clocks array here and remove the
redundant s3c_register_clocks call for init_clocks in s3c2443_init_clocks.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S3C2443 uses hsmmc1 as its only hsmmc device and for S3C2416/S3C2450
it's the second hsmmc channel with the same PCLKCON bit.
The hsmmc-if clocks on both systems already got a devname, as did
the hsmmc pclk for hsmmc0 on the S3C2416. So to make it possible to
identify the hsmmc1 pclk on S3C2416 add the correct devname for it.
The sclk name on S3C2443 also is s3c-sdhci.1.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.
This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Cpufreq uses frequencies in kHz and not Hz, so set_rate and round_rate
would be called with a frequency of 266666000 instead of 266666666 but
the clock functions check for rates smaller or equal to the targetrate.
As the armdiv does not support steps this small we can accommodate
this by simply also setting the last 3 digits of the calculated rate
to zero.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The armdiv array may contain unset divider values.
Check the relevant value to prevent division by zero
errors. Also check for set nr_armdiv and armdivmask
before meddling with clkdiv0.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The system-layout of the armdiv and armclk is common to
S3C2443/S3C2416/S3C2450 and only differs in the array of
possible dividers. Therefore it is possible to reuse the
clock definitions for all of these SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
