The current limit is small for Android Things Verity Boot args.
Bump it.
Change-Id: I091c7f6d4912fec57ecca7dcab38cc99c5b6dfb5
Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
The default parent of i2s_src is 200MHz CPLL, it doesn't meet
the constraint of fractional divider that denominator must be
20 times larger than numerator.
Change-Id: I986525ca7a92cb5883facd1b6e89079398302856
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Change-Id: I9b3d30eca632d3cfb958f0b31c067f4a6af2d631
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: linux-leds@vger.kernel.org
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
(cherry picked from commit 0571753e65)
Otherwise the driver module will not be automatically probed.
Change-Id: I14c8ee83ed97c3f08013c6aceb1f2c8889afcd94
Fixes: 9d7cffaf99 ("leds: Add driver for the ISSI IS31FL32xx family of LED controllers")
Fixes: e0442d7def ("leds: Add SN3218 and SN3216 support to the IS31FL32XX driver")
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: David Rivshin <drivshin@allworx.com>
Acked-by: David Rivshin <drivshin@allworx.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
(cherry picked from commit 5706c01fcf)
The IS31FL32xx family of LED controllers are I2C devices with multiple
constant-current channels, each with independent 256-level PWM control.
Datasheets: http://www.issi.com/US/product-analog-fxled-driver.shtml
This has been tested on the IS31FL3236 and IS31FL3216, on an ARM
(TI am335x) platform.
The programming paradigm of these devices is similar in the following
ways:
- All registers are 8 bit
- All LED control registers are write-only
- Each LED channel has a PWM register (0-255)
- PWM register writes are shadowed until an Update register is poked
- All have a concept of Software Shutdown, which disables output
However, there are some differences in devices:
- 3236/3235 have a separate Control register for each LED,
(3218/3216 pack the enable bits into fewer registers)
- 3236/3235 have a per-channel current divisor setting
- 3236/3235 have a Global Control register that can turn off all LEDs
- 3216 is unique in a number of ways
- OUT9-OUT16 can be configured as GPIOs instead of LED controls
- LEDs can be programmed with an 8-frame animation, with
programmable delay between frames
- LEDs can be modulated by an input audio signal
- Max output current can be adjusted from 1/4 to 2x globally
- Has a Configuration register instead of a Shutdown register
This driver currently only supports the base PWM control function
of these devices. The following features of these devices are not
implemented, although it should be possible to add them in the future:
- All devices are capable of going into a lower-power "software
shutdown" mode.
- The is31fl3236 and is31fl3235 can reduce the max output current
per-channel with a divisor of 1, 2, 3, or 4.
- The is31fl3216 can use some LED channels as GPIOs instead.
- The is31fl3216 can animate LEDs in hardware.
- The is31fl3216 can modulate LEDs according to an audio input.
- The is31fl3216 can reduce/increase max output current globally.
Change-Id: Ie82c99ec43dbbd3175fb29f224812f3b5dc92eb6
Signed-off-by: David Rivshin <drivshin@allworx.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
(cherry picked from commit 9d7cffaf99)
The es8328 drivers seems to have used the wm8753 driver as a template. Its
header file contains a few defines that are copied verbatim from the wm8753
header that do not really apply to this driver and are unused. So remove
those defines. This seems safe as they deal with PLL and clock divider
settings and the es8328 driver neither implements a set_pll() nor a
set_clkdiv() callback.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 0f40132)
Change-Id: I1c4c93dd3335678942c19693b0844d9152c7197b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The master and slave modes don't share the same table for MCLK/LRCLK
ratios. The slaves mode has bigger ratios that allow to use BCLK that
matche sampling frequency of 192khz.
This commit enables this rate only for slave mode, i.e it does not
declare this frequency in sysclk_contraints, resulting to an error in
master mode (not supported CLK).
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 404785f)
Change-Id: I6bee5d4605a7612eac0a955c52bf80c500adbc5b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Currently most of the standard rates are supported by this driver.
Instead of defining each supported rate one by one, we use the SND macro
SNDRV_PCM_RATE_8000_48000. Also adds support for 88.2khz as the codec
supports it and the sys clocks are already supported.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit c7ad841)
Change-Id: I8b98cb6fc4aef7a3eb6e22310872668c2046ba46
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
In master mode, SCLK and LRCLK signals are generated by the CODEC when
any of the ADC/DAC are enabled. SCLK is derived from MCLK via a
programmable division set by BLK_DIV, LRCLK is derived from MCLK via
another programmable division set by ADCFsRatio/DACFsRatio.
In slave mode, SCLK and LRCLK signals are received as inputs and
supplied externally. LRCLK and SCLK must be synchronously derived from
MCLK with specific rates. The device can auto detect MCLK/LRCLK ratio
according to a predefined table. LRCLK/SCLK ratio is usually 64 (SCLK =
64 * LRCLK)
This commits adds support to let to device auto detect and decide which
ratio to use. The mclkdiv2 and BCLK_DIV ratio and put to zero.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit ae884ae)
Change-Id: I195d5c3fc9f8b3032c5f0a1c767da696de22fb9b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Currently, the function that changes the DAI format only supports master
mode. Trying to use a slave mode exits the function with -EINVAL and
leave the codec misconfigured. This commits adds support for enabling
the slave mode.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit b9b044e)
Change-Id: Iae229b7504df9567ca374a1e47555b45ba76dc5d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
codec driver and component driver has duplicated callback functions,
and codec side functions are just copied to component side when
register timing. This was quick-hack, but no longer needed.
This patch moves these functions from codec driver to component driver.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 87869e4)
Change-Id: I6cb19b9a2febba1802872caf6883013aeb5e3504
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Although the ES8328 does support different rates for capture and
playback, only very limited combinations are supported (8kHz and 48kHz
or 8.0182kHz and 44.1kHz) with most rates required to be symmetric.
Instead of adding a lot of complexity for little gain, let's enforce
symmetric rates.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit ca0d879)
Change-Id: If155a5d6efa318f03226862a26d519b804c10004
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The values are the same for the DAC and ADC so remove the specific
values and use values with shifts.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 779e86a)
Change-Id: Ic3bbe56ae7aaa1c11112769646451ce593974352
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
This is a refactor in preparation for supporting more sample sizes which
has no functional change.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 8865c95)
Change-Id: I05c62052a573a5d24d8b91c385ef19b13ee56b49
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The chip only supports single reads and writes.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit f2ed04a)
Change-Id: Id70c848dfea948df11517bc6112c314878dcc9ca
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The ADCCONTROL4 and DACCONTROL1 registers are similar but not identical,
with the DACCONTROL1 having each field starting one bit higher than
ADCCONTROL4.
Instead of introducing a magic shift, add new constants for the values
in ADCCONTROL4 and use a second variable to setup the ADC.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 57e41f3)
Change-Id: I2e34c6671d38505700b987f34af53c4134702b75
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
This ensures that the clock is setup after its frequency has been set;
the existing code in set_dai_fmt may be called before the clock rate has
been set resulting in an incorrect configuration.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 420c470d)
Change-Id: Ib963bd5cfb09da397afa90ac628af8b775da821c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: Ia5a7e0c8bcdcc33880f6048d71068a5ccb1c042e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
(cherry picked from commit ae98ee15abc476711d04b5885848ee6570ee816d)
The driver will check cmdline mtd partition table first,
if there is no mtd partition table, then the driver will
add nand block device and set gd flag GENHD_FL_EXT_DEVT.
Change-Id: I262c935a2fac89c2a203dac9b8e90133317860f8
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
Currently we are trying to enable/disable the clk of irq's gpio bank when
unmask/mask irq. But the kernel's "lazy disable approach" will skip masking
irq when the irq chip doesn't support irq_disable ops.
So we may hit this case:
irq_enable-> enable clk
irq_disable-> noop
irq_enable-> enable clk again
irq_disable-> noop
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit d468289a02)
Change-Id: Ibe2f5c4ef48425300355a46312215984d8f4e1bc
when the work clock is the same as the bus clock.drop
the "clock-names" property as the PWM uses only one
clock (the driver now needs to call devm_clk_get with NULL).
Change-Id: I7fcdd9635f81778a3dc522d99d0fc081408d6fea
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
Introduce status node in debugfs to show HDMI output status,
such as phy status, color and eotf.
Here is a sample log:
PHY enabled Mode: HDMI
Pixel Clk: 594000000Hz TMDS Clk: 594000000Hz
Color Format: YUV422 Color Depth: 10 bit
Colorimetry: ITU.BT2020 EOTF: ST2084
x0: 0 y0: 0
x1: 0 y1: 0
x2: 0 y2: 0
white x: 0 white y: 0
max lum: 0 min lum: 0
max cll: 0 max fall: 0
Change-Id: I5d458b633dd3bd9aab67cc91f1695621937e58f5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
