Not only the edp 24m clock domain need software reset,
the edp ctrl apb bus of rk3368 also need software reset before request irq.
Signed-off-by: chenyifu <chenyf@rock-chips.com>
In order to provide low jitter dclk_lcdc for dislay(especially HDMI),
we neeed to set dclk_lcdc's src pll with max VCO. Thus we add
clk_pll_ops_3368_low_jitter type pll to get pll low jitter setting
from a table. Also dclk_lcdc ops in rk3368 is modifided to get best
parent rate from a table firstly, or caculate a parent rate if not
found in the table.
Signed-off-by: dkl <dkl@rock-chips.com>
Disable iommu when decoding failure, so the iommu could
restore its state when the decoding resume.
Without this step, iommu will work in invalid state.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
<4>[ 4109.549723] [<c0013e24>] (unwind_backtrace+0x0/0xe0) from [<c001172c>] (show_stack+0x10/0x14)
<4>[ 4109.549737] [<c001172c>] (show_stack+0x10/0x14) from [<c0032408>] (warn_slowpath_common+0x4c/0x68)
<4>[ 4109.549750] [<c0032408>] (warn_slowpath_common+0x4c/0x68) from [<c00324a4>] (warn_slowpath_fmt+0x2c/0x3c)
<4>[ 4109.549762] [<c00324a4>] (warn_slowpath_fmt+0x2c/0x3c) from [<c009899c>] (watchdog_check_hardlockup_other_cpu+0xd0/0xf8)
<4>[ 4109.549778] [<c009899c>] (watchdog_check_hardlockup_other_cpu+0xd0/0xf8) from [<c00989fc>] (watchdog_timer_fn+0x38/0x168)
<4>[ 4109.549793] [<c00989fc>] (watchdog_timer_fn+0x38/0x168) from [<c0054c7c>] (__run_hrtimer+0x1a4/0x2b8)
<4>[ 4109.549807] [<c0054c7c>] (__run_hrtimer+0x1a4/0x2b8) from [<c005587c>] (hrtimer_interrupt+0x11c/0x278)
<4>[ 4109.549830] [<c005587c>] (hrtimer_interrupt+0x11c/0x278) from [<c056b65c>] (arch_timer_handler_phys+0x28/0x30)
<4>[ 4109.549846] [<c056b65c>] (arch_timer_handler_phys+0x28/0x30) from [<c009c3a4>] (handle_percpu_devid_irq+0xf8/0x1b4)
<4>[ 4109.549861] [<c009c3a4>] (handle_percpu_devid_irq+0xf8/0x1b4) from [<c0098fa4>] (generic_handle_irq+0x20/0x30)
<4>[ 4109.549872] [<c0098fa4>] (generic_handle_irq+0x20/0x30) from [<c000e3ac>] (handle_IRQ+0x64/0x8c)
<4>[ 4109.549883] [<c000e3ac>] (handle_IRQ+0x64/0x8c) from [<c0008538>] (gic_handle_irq+0x34/0x58)
<4>[ 4109.549893] [<c0008538>] (gic_handle_irq+0x34/0x58) from [<c000d600>] (__irq_svc+0x40/0x70)
<4>[ 4109.549901] Exception stack(0xed0addd8 to 0xed0ade20)
<4>[ 4109.549910] ddc0: 00000003 00000000
<4>[ 4109.549920] dde0: 00000003 c0c5bff3 c0c5bff0 c0c5bff0 547b152f 000003c8 00000000 c0b8446c
<4>[ 4109.549930] de00: ed0ade48 83126e97 00000003 ed0ade20 c0023638 c00235ec 600f0113 ffffffff
<4>[ 4109.549941] [<c000d600>] (__irq_svc+0x40/0x70) from [<c00235ec>] (call_with_single_cpu.isra.4+0x9c/0x154)
<4>[ 4109.549952] [<c00235ec>] (call_with_single_cpu.isra.4+0x9c/0x154) from [<c0023820>] (_ddr_change_freq+0x17c/0x1c0)
<4>[ 4109.549963] [<c0023820>] (_ddr_change_freq+0x17c/0x1c0) from [<c0025088>] (ddrfreq_scale_rate_for_dvfs+0x20/0x74)
<4>[ 4109.549978] [<c0025088>] (ddrfreq_scale_rate_for_dvfs+0x20/0x74) from [<c002937c>] (dvfs_target+0x15c/0x204)
<4>[ 4109.549993] [<c002937c>] (dvfs_target+0x15c/0x204) from [<c0027d70>] (dvfs_clk_set_rate+0x44/0x80)
<4>[ 4109.550007] [<c0027d70>] (dvfs_clk_set_rate+0x44/0x80) from [<c00252a0>] (ddrfreq_mode.part.3+0x40/0xec)
<4>[ 4109.550017] [<c00252a0>] (ddrfreq_mode.part.3+0x40/0xec) from [<c00257c0>] (ddrfreq_work+0x184/0x1d4)
<4>[ 4109.550029] [<c00257c0>] (ddrfreq_work+0x184/0x1d4) from [<c0025868>] (ddrfreq_task+0x58/0x1b8)
<4>[ 4109.550041] [<c0025868>] (ddrfreq_task+0x58/0x1b8) from [<c0051ad4>] (kthread+0xa0/0xac)
<4>[ 4109.550054] [<c0051ad4>] (kthread+0xa0/0xac) from [<c000da98>] (ret_from_fork+0x14/0x3c)
<4>[ 4092.709215] CPU: 2 PID: 17844 Comm: mali-utility-wo Not tainted 3.10.0 #136
<4>[ 4092.709408] [<c0037494>] (mm_update_next_owner+0xc4/0x1c0) from [<c0037704>] (exit_mm+0x174/0x184)
<4>[ 4092.709422] [<c0037704>] (exit_mm+0x174/0x184) from [<c0037918>] (do_exit+0x204/0x400)
<4>[ 4092.709433] [<c0037918>] (do_exit+0x204/0x400) from [<c0037bc8>] (do_group_exit+0x88/0xb4)
<4>[ 4092.709447] [<c0037bc8>] (do_group_exit+0x88/0xb4) from [<c00444b0>] (get_signal_to_deliver+0x3b4/0x3fc)
<4>[ 4092.709459] [<c00444b0>] (get_signal_to_deliver+0x3b4/0x3fc) from [<c0010c00>] (do_signal+0xa0/0x14c)
<4>[ 4092.709469] [<c0010c00>] (do_signal+0xa0/0x14c) from [<c0010fa4>] (do_work_pending+0x4c/0x94)
<4>[ 4092.709480] [<c0010fa4>] (do_work_pending+0x4c/0x94) from [<c000da40>] (work_pending+0xc/0x20)
cpu0 is waiting for the other cpu respond ipi, but one cpu is blocked on getting &tasklist_lock
while irq is disabled and it will not respond ipi. If all the operation of &tasklist_lock is irq-disabled,
the &tasklist_lock will become available before the owner respond ipi, so the blocked cpu will get the
&tasklist_lock.
Signed-off-by: cl <cl@rock-chips.com>
On Cortex-A12 (r0p0, r0p1), in very rare timing conditions, a sequence of
VMOV to Core registers instructions, for which the second one is in the
shadow of a branch or abort, can lead to a deadlock when the VMOV
instructions are issued out-of-order. This workaround setting bit 1 of
the Internal Feature Register prevents the erratum.
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
For we don't use charge display function in 3.10 kernel, when
android write 0 to /sys/class/android_usb/android0/enable no need
to set pcd->conn_status = 2 and gating usb clocks.
Signed-off-by: lyz <lyz@rock-chips.com>
no power domain on rk3036, but trying to enable the power
domain in previous driver code. remove the power domain
enable in this revision on rk3036 platform.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
The commit 28e9901cf0 set
otg device phy enter suspend and resume it after system
wakeup. But we don't control the clk, and it will cause
otg device repeatedly disable clk when resume from suspend.
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
