1. switch to normal pll(200M) before disable pd.
2. call pm_runtime_get() to enable pd before change freq(pvtpll).
Change-Id: I8749025c42ec40604361db4d4de2c2b819e0b2a3
Signed-off-by: Liang Chen <cl@rock-chips.com>
Tuing pre-emphasis and turn off differential receiver in suspend mode
for rk3326s and px30s SoCs.
Fix some pc can not recognize the device when using 5m cable, so tuning
usb phy squelch trigger point configure to 100mv for px30s.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ida216e8951c1f1dad19fa3ff4c31ede6a53b3458
disable pin_txclkesc inverting.
reset digital logic before select lvds mode.
add support 2.5Gsps lane rate for px30s.
reset digital logic before select TTL mode.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I275d589f56e5963649aee9397eba3a9994e5901d
PX30s has 3bit for drive strength set, the highest bit is from slewrate
bit used on PX30.
Change-Id: I21085cb10247eff9c92979ac24449759b0677b34
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There are two Temperature Sensor on px30s, channel 0 is for CPU,
channel 1 is for GPU.
set trim for px30s.
Change-Id: I25e16c8d398634d83a3611fa829ee2e9dd974538
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This adds the necessary data for handling efuse on the px30s.
Change-Id: Iaa509d8d22102ff4d054e855d330792f0da8f382
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The value of bit[15:14] in DDR_GRF_BASE1 define px30/px30s.
px30: bit[15:14]=0x00
px30s: bit[15:14]=0x03
Change-Id: I07e31e8fd56ee2eea7883a5f5de012740ec0e98a
Signed-off-by: Liang Chen <cl@rock-chips.com>
use tid_name to singed buf user, so we can check buf usage, and recyle
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: Iccf48bc30fbbf1ab44ac33babc9f00500b647623
ebc power on in advance
fix resume check not drop buf
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I1f34d4c5bd49a730967c997225f40dbed165bc92
Some PC USB Hosts (e.g Dell laptop) fail to send
SetInterface(AltSet=0) to stop capture/playback
when PC enter suspend or play YouTube Video.
To be compatible with these PC, add this patch to
stop capture/playback prior to start again if the
stream_state is true.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iced57de39b6b88a7c987897dcb123cf8d7cf6473
Some times we want change a overlay plane defined in vop2_reg
to primary plane.
Change-Id: I5f563fb258a66278255be762ebdfca21b51aabd1
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
rk3568 rkvdec2 link mode should setup clock to max frequency on power on
stage and keep the frequency unchanged until power off.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I2a69f6d8b0a50c399f408320ca2b9bc4539b768a
This can be used by Type-C controller drivers which use a standard
usb-connector fwnode, with altmodes sub-node, to describe the available
altmodes.
Note there are is no devicetree bindings documentation for the altmodes
node, this is deliberate. ATM the fwnodes used to register the altmodes
are only used internally to pass platform info from a drivers/platform/x86
driver to the type-c subsystem.
When a devicetree user of this functionally comes up and the dt-bindings
have been hashed out the internal use can be adjusted to match the
dt-bindings.
Currently the typec_port_register_altmodes() function expects
an "altmodes" child fwnode on port->dev with this "altmodes" fwnode having
child fwnodes itself with each child containing 2 integer properties:
1. A "svid" property, which sets the id of the altmode, e.g. displayport
altmode has a svid of 0xff01.
2. A "vdo" property, typically used as a bitmask describing the
capabilities of the altmode, the bits in the vdo are specified in the
specification of the altmode.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20210409134033.105834-2-hdegoede@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Change-Id: Ib78f0b67b985751a32b6f42e79c7976f5515f6b2
Signed-off-by: zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
(cherry picked from commit 9cf9c33b76)
intx_lock should be initialized before use.
Fixes: ee99fe07a7 ("PCIe: rockchip: Add more legacy int support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I39586ae4f8edc1c39d78ce95af29f24bfc46b4d4
1. mpp_iommu_refresh will crash after mpp_iommu_detach, cause by
iommu->domain is null.
2. After the mpp_iommu_refresh operation, there is no need to do
mpp_iommu_detach/attach operations, because the purpose is the same
for refresh iommu.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I7c39a63cac67e94b80e7df26c8962b3fed4c670e
Some vendor drivers rely on flow control by toggling
enable/disable virtual irq if using legacy interrupt.
It can certainly change the behaviour by function
drivers, but adding corresponding operations would make
RC driver more flexible.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idf3e6a0ca9c4ebde369745713a88db53e3f72ea5
The utmi clk is provided by the USB PHY for the USB controller.
And the utmi clk is disabled if the USB PHY enter suspend mode.
The current charge detection sets the USB PHY in suspend mode
at first, then take about hundreds of milliseconds to do charge
detection, in other words, the utmi clk will be disabled hundreds
of milliseconds. It may cause the USB controller work abnormally
during the charge detection.
Actually, the conditions for charger detection is:
1. Set the utmi_opmode in non-driving mode.
2. Set the utmi_xcvrselect to FS speed.
3. Set the utmi_termselect to FS speed.
4. Enable the DP/DM pulldown resistor.
This patch adds a new chg_mode to set the PHY in charge detection
mode according to the above conditions, and set the PHY in normal
mode to keep the utmi clk at the same time.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1cbf565d5145bdae5bc91132bc5fbff23a5cc443
For Husb311, ET7303 and other PD chips, the tcpm framework is used.
In order not to modify the usb controller, usb3.0 phy and DP
driver, the extcon notify mechanism is added.
Change-Id: I02552d5a2d1d2491ff9a647ca1a85e75e295ebd2
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
We should avoid rolling the phases if 270 and 0 is both
fine in tuning. Otherwise it would chose a middle phase
laid later than 270 which isn't a good.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Fixes: 8d0e882790 ("mmc: dw_mmc-rockchip: Skip all phases bigger than 270 degrees")
Change-Id: I87bd3e957623d6a5fdf38226be65564e353b01b6
slot's clock is cached before calling ->set_ios for sub-driver.
If the clock is updated by sub-driver, it's better to restore
the cached slot's clock. Or we can see a unexpected clock as the
driver didn't know the slot's clock is updated and still use the
old clock to calculate divider. So we may see a lower clock. It
theory, it's won't be a problem because any rate lower than 400k
should be fine, and we even didn't start issuing any command during
the lower clock. But still it's right to update slot's clock to reflect
the correct clock and may fix some potential unknown problems.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I06581320547bb06c306da57e141d06f9206ea585
