There is a RGB output port on rv1126, add documentation for it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I012cafc394b3056b5deba46350d99635b7dc9b5a
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Change-Id: I16ae0f862cc4d56aac24b0b5011e393a92641cdf
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
RV1126 is a high-performance vision processor SoC, especially
for AI related application. RV1109 is much similar to RV1126,
except for the number of cpu cores and some features.
Change-Id: I4834387c94f7b4d7536232e3b53ad7e716431e3e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Add constants and callback functions for the dwmac on RV1126 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Because the gmac driver does not know whether pinctrl is
configured with m0 or m1 at this time, so we configure the
delayline of m0 and m1 at the same time.
Change-Id: I3bf58f30584f91c53dd98f747b2d5a2e3f32c505
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
RV1126 tsadc bandgap chopper function should be configed,
add a new initialize function to handle this for RV1126 SoCs.
RV1126 tshut mode also need select the tshut type in GRF regs,
add a new set mode function to handle this for RV1126 SoCs.
Change-Id: I81106539362bc32e0d8aaeeb0398d1bcb33b6b60
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RV1126 SOC has two independent Temperature Sensors for CPU and NPU.
RV1126 TSADC clock design has been updated, added the PHY clock,
using the group managed clocks.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I395daa3b591390980a11ea7eed827c0e297f6ebe
Add a new compatible for thermal founding on RV1126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I84e7ca521f4edce9516575bd54709326e62fc85c
This driver is modified to support RV1126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I1a3c87d9b17b198e5cf5408b732b2a53363f4ef1
Add binding documentation for the power domains
found on Rockchip RV1126 SoCs.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Icf38d7a8fa44abf119e57a66ceddc1a01872facf
The gpio v2 has some new features:
- Use mask bit for register write;
- Both edge intterupt supported;
- longer debounce time for input intterupt.
Change-Id: I61f3974d2e0cf0e93c686aa11cd35162e59f393b
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add the clock tree definition for the new RV1126 SoC.
Change-Id: I4a329d27d3a84f43a0ae956bce16597706eeb1ae
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
There is a new clock branch have a form like
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|-----[GATE]--[DVI]------| \
---[HPLL]---| / | |mux|--[GATE]--
|--/ |--[GATE]--[HALFDVI]--| /
|--/
This patch registers two composite clocks for this branch type,
and make them become brother clock for each oher.
Change-Id: I46aeab26e478f341600114014db1c7d58e234f11
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Some composite clocks may have the same parent clock, if one clock change
the parent clock rate, the other clock rate may too large, so add a
brother clock in composite that the other clock also can be changed when
parent rate is changed.
Change-Id: I2c6749e578b76d6780cecdcd9ff1b5fd4f25a0ba
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This reverts commit d13501a2be.
This patch causes 32768Hz can't be divided from 24MHz.
Change-Id: I1e86c2b0c96be0d1a80de83d1ac5e5909becbde1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The edp_hpd pin had the conflict with the hdmi cec, enable the hdmi-cec
by default.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Id129364c352377c59f2b2ff48dd97ffefaf6af11
Most users used 4K monitors with HDMI on RK3399/RK3399PRO platform, but no
more than 2K monitors on EDP/DSI panels.
So the reasonable that HDMI connected to VOPB control, and EDP/DSI shound
be connected to VOPL.
Change-Id: Id97efc5d6d534c302aa52ad00e705c093457f41e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
There is a problem that incorrectly advances the TRB dequeue
pointer if more than one request in the started_list need to
be dequeue. If the request was already started, we issue the
END_TRANSFER command, then wait for END_TRANSFER completion
and only after that jump over the TRBs of the request by
clearing HWO and incrementing the TRB dequeue pointer. But we
don't skip over the TRBs of the rest started request, this
cause we to get incorrect TRB dequeue pointer on completion
next time.
We can easily reproduce this problem on RK3399 EVB Android Q
platform. Use MTP/PTP to transfer a big file, and then cancel
the transition, check if it can transfer again. If retransmission
fails, the problem happens. And if you enable the DWC3 trace
via tracing interface:
echo 1 > /sys/kernel/debug/tracing/events/dwc3/enable
You can get the error log:
irq/71-dwc3-1591 [000] d..1 389.337189: dwc3_complete_trb: ep1out: trb 00000000213b87d9 buf 00000000a84c0000 size 16384
irq/71-dwc3-1591 [000] d..1 389.337195: dwc3_gadget_giveback: ep1out: req 00000000d8c093a2 length 4294951424/512 zsI ==> 0
...
kworker/u12:2-111 [003] .... 389.337380: dwc3_free_request: ep1out: req 00000000d8c093a2 length 4294951424/512 zsI ==> 0
The req actual length is error. It's because that it get the
incorrect TRB dequeue pointer that belong to previous request.
Change-Id: I123ff779d5e2933449581f8b570e2e6ad6b75458
Signed-off-by: William Wu <william.wu@rock-chips.com>
