Change spelling of 'associcated' to 'associated', to fix the spelling
mistake.
Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Fix indentation for switch-case statements to fix following
checkpatch.pl Error:
ERROR: switch and case should be at the same indent
Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
As caller rdev_set_default_key not particular about -EFAULT.
We can preserve the return value of prism2_domibset_uint32.
Signed-off-by: Hariprasad Kelam <hariprasad.kelam@gmail.com>
Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
----
Changes in v2:
- remove masking of original return value with EFAULT
Changes in v3:
- merge patch v1 and v2 sothat it can be applied on linux-next
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
i.MX8MM has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SX SDB board, vgen6 supplies vdd1p1/vdd2p5 LDO and
sw2 supplies vdd3p0 LDO, this patch assigns corresponding power
supply for vdd1p1/vdd2p5/vdd3p0 to avoid confusion by below log:
vdd1p1: supplied by regulator-dummy
vdd3p0: supplied by regulator-dummy
vdd2p5: supplied by regulator-dummy
With this patch, the power supply is more accurate:
vdd1p1: supplied by VGEN6
vdd3p0: supplied by SW2
vdd2p5: supplied by VGEN6
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SLL EVK board, sw2 supplies vdd3p0 LDO, this patch assigns
corresponding power supply for vdd3p0 to avoid confusion by below log:
vdd3p0: supplied by regulator-dummy
With this patch, the power supply is more accurate:
vdd3p0: supplied by SW2
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SL EVK board, sw2 supplies vdd1p1/vdd2p5/vdd3p0 LDO, this
patch assigns corresponding power supply for vdd1p1/vdd2p5/vdd3p0
to avoid confusion by below log:
vdd1p1: supplied by regulator-dummy
vdd3p0: supplied by regulator-dummy
vdd2p5: supplied by regulator-dummy
With this patch, the power supply is more accurate:
vdd1p1: supplied by SW2
vdd3p0: supplied by SW2
vdd2p5: supplied by SW2
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX7D SDB board, sw2 supplies 1p0d/1p2 LDO, this patch assigns
corresponding power supply for 1p0d/1p2 LDO to avoid confusion by
below log:
vdd1p0d: supplied by regulator-dummy
vdd1p2: supplied by regulator-dummy
With this patch, the power supply is more accurate:
vdd1p0d: supplied by SW2
vdd1p2: supplied by SW2
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6Q/DL SabreSD board, vgen5 supplies vdd1p1/vdd2p5 LDO and
sw2 supplies vdd3p0 LDO, this patch assigns corresponding power
supply for vdd1p1/vdd2p5/vdd3p0 to avoid confusion by below log:
vdd1p1: supplied by regulator-dummy
vdd3p0: supplied by regulator-dummy
vdd2p5: supplied by regulator-dummy
With this patch, the power supply is more accurate:
vdd1p1: supplied by VGEN5
vdd3p0: supplied by SW2
vdd2p5: supplied by VGEN5
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The BUCK2 regulator is used for cpufreq voltage control, otherwise
configuration is mostly static.
This uses the newly-implemented rohm,reset-snvs-powered property to
properly handle the SNVS state of imx8mm.
Between BD71837 and BD71847 the BUCK3/4 regulators were removed but
datasheet and board schematics kept the names for BUCK5/6/7/8. The
driver however renumbered 5/6/7/8 to 3/4/5/6. Use the names from DT
bindings and add comments to signal this.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-By: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
During randconfig builds, I occasionally run into an invalid configuration
drivers/soc/imx/soc-imx8.o: In function `imx8_soc_init':
soc-imx8.c:(.init.text+0x144): undefined reference to `soc_device_register'
while CONFIG_SOC_BUS is not set, the building failed like this. This patch
selects SOC_BUS to fix it.
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: a7e26f356c ("soc: imx: Add generic i.MX8 SoC driver")
Suggested-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The LS1028A has a LCD controller and Displayport interface that
connects to eDP and Displayport connectors on the LS1028A board.
This patch enables the LCD controller driver on the LS1028A.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX6SL's KPP and WDOG use IMX6SL_CLK_IPG as clock root,
assign IMX6SL_CLK_IPG to them instead of IMX6SL_CLK_DUMMY.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable mfd and regulator driver for PMIC found on imx8mm-evk boards
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The current lpi2c driver can work on imx8 chips so lets enable it. Also
enable few i2c peripherals found on imx8qxp-mek I2C (some were already
used for other boards).
Sensors enabled as modules because not required for boot.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Basic imx8mm support is already available in linux-next just not
enabled in arm64 defconfig. With this patch imx8mm-evk can boot.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable CONFIG_IMX_SC_WDT as module to support i.MX system
controller watchdog.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that there is a board making use of this bus is available
enable the siox code to increase compile coverage.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The imx6q-logicpd board has a PCF8575 connected to it, so this
patch turns it on my default now.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable the CONFIG_SPI_IMX option so that i.MX8M can use the
imx spi driver by default.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Kernel booted just with ima_policy=tcb (not with
ima_policy=appraise_tcb) shouldn't require signed policy.
Regression found with LTP test ima_policy.sh.
Fixes: c52657d93b ("ima: refactor ima_init_policy()")
Cc: stable@vger.kernel.org (linux-5.0)
Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
Checking efi_enabled(EFI_BOOT) is not sufficient to ensure that
EFI runtime services are available, e.g. if efi=noruntime is used.
Without this, I get an oops on a PREEMPT_RT kernel where efi=noruntime is
the default.
Fixes: 399574c64e ("x86/ima: retry detecting secure boot mode")
Cc: stable@vger.kernel.org (linux-5.0)
Signed-off-by: Scott Wood <swood@redhat.com>
Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
Add missing 1.464GHz clock rate to rk3228_cpuclk_rates[], which gets
referenced in the operating points but wasn't defined till now.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There's a bit of math in rockchip_mmc_get_phase() to calculate the
"fine delay". This math boils down to:
PSECS_PER_SEC = 1000000000000.
ROCKCHIP_MMC_DELAY_ELEMENT_PSEC = 60
card_clk * ROCKCHIP_MMC_DELAY_ELEMENT_PSEC * 360 * x / PSECS_PER_SEC
...but we do it in pieces to avoid overflowing 32-bits. Right now we
overdo it a little bit, though, and end up getting less accurate math
than we could. Right now we do:
DIV_ROUND_CLOSEST((card_clk / 1000000) *
(ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
(360 / 10) *
delay_num,
PSECS_PER_SEC / 1000000 / 10 / 10)
This is non-ideal because:
A) The pins on Rockchip SoCs are rated to go at most 150 MHz, so the
max card clock is 150 MHz. Even ignoring this the maximum SD card
clock (for SDR104) would be 208 MHz. This means you can decrease
your division by 100x and still not overflow:
hex(208000000 / 10000 * 6 * 36 * 0xff) == 0x44497200
B) On many Rockchip SoCs we end up with a card clock that is actually
148500000 because we parent off the 297 MHz PLL. That means the
math we're actually doing today is less than ideal. Specifically:
148500000 / 1000000 = 148
Let's fix the math to be slightly more accurate.
NOTE: no known problems are fixed by this. It was found simply by
code inspection. If you want to see the difference between the old
and the new on a 148.5 MHz clock, this python can help:
old = [x for x in
(int(round(148 * 6 * 36 * x / 10000.)) for x in range(256))
if x < 90]
new = [x for x in
(int(round(1485 * 6 * 36 * x / 100000.)) for x in range(256))
if x < 90]
The only differences are:
delay_num=17 54=>55
delay_num=22 70=>71
delay_num=27 86=>87
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
At boot time, my rk3288-veyron devices yell with 8 lines that look
like this:
[ 0.000000] rockchip_mmc_get_phase: invalid clk rate
This is because the clock framework at clk_register() time tries to
get the phase but we don't have a parent yet.
While the errors appear to be harmless they are still ugly and, in
general, we don't want yells like this in the log unless they are
important.
There's no real reason to be yelling here. We can still return
-EINVAL to indicate that the phase makes no sense without a parent.
If someone really tries to do tuning and the clock is reported as 0
then we'll see the yells in rockchip_mmc_set_phase().
Fixes: 4bf59902b5 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
When calculating the MMC phase we can just use clk_hw_get_rate()
instead of clk_get_rate(). This avoids recalculating the rate.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The call to of_get_next_child returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
./arch/arm/mach-rockchip/pm.c:269:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 259, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/pm.c:275:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 259, but without a corresponding object release within this function
./arch/arm/mach-rockchip/platsmp.c:281:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 272, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/platsmp.c:285:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 272, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/platsmp.c:289:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 272, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/platsmp.c:303:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 294, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:
CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable SPI0 and SPI4 exposed on the Low and High speed expansion
connectors of Rock960.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Raise the temperature of the GPU thermal trip point for speedy
to 80°C. This is the value used by the downstream Chrome OS 3.14
kernel, the 'official' kernel for speedy.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The values match those used by the downstream Chrome OS 3.14
kernel, the 'official' kernel for veyron devices. Keep the critical
trip point for speedy at 90°C as in the downstream configuration.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
