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https://github.com/hardkernel/linux.git
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311 lines
7.1 KiB
ArmAsm
Executable File
311 lines
7.1 KiB
ArmAsm
Executable File
#include <linux/linkage.h>
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#include <asm/memory.h>
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#include <asm/glue.h>
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#include <asm/vfpmacros.h>
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#include <asm/thread_notify.h>
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#include <asm/ptrace.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <mach/rk29_iomap.h>
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#__scu_call_wrap:
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#
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# call to the defined funcion.
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# r0: func argument array , max = 6
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# r1: argument num.
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# r2: the function number.
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#; EXPORT __scu_call_wrap
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#;
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#; CODE32
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#; AREA ||funwrap||, CODE, READONLY
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ENTRY(__scu_call_wrap)
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STMFD r13!,{r4,r5,r6,lr}
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mov r6,r2
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ldmia r0, {r0-r5}
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STMFD r13!,{r4,r5}
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mov lr , pc
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mov pc , r6
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add r13 , r13 ,#8
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LDMFD r13!,{r4,r5,r6,pc}
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/**
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* 20091126,HSL@RK,change to get syscall struct pt_regs *.
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* way: search stack frame for lr = ret_fast_syscall.
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* code from bachtrace.S -- __backtrace.
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* 20110126,not support at 2.6.32(no fp)
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* 20110127,support at debug.c,use c funtion.
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*/
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#define frame r4
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#define sv_fp r5
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#define sv_pc r6
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#define mask r7
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#define offset r8
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/*
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ENTRY(__scu_get_usr_regs)
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mov r0, #0
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mov pc, lr
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*/
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/*
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* 20091215,continue running from break point.
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* r0 is the struct pt_regs *.
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*/
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ENTRY(__scu_bk_continue)
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mov r12, r0
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ldr r0, [r12, #S_PSR]
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msr spsr_cxsf, r0
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ldmia r12, {r0 - pc}^ @ load r0 - pc, cpsr
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ENTRY(__run)
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mov r0, r0
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mov pc, lr
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/* 20110212,HSL@RK, USE parm0 for debug.
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*
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*/
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ENTRY(__rb)
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mov r7,r0
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/* adr r0 , __rb_info
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adr r8, __prk
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ldr r8,[r8,#0]
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adr r1 , __rb
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mov lr , pc
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bx r8
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mov r0,#0x10000
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bl __rb_delay
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*/
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mov r8,r7
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/* adr r0 , __prk_info
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1:
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ldrb r1,[r0],#1
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cmp r1,#0
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strne r1,[r8,#0]
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bne 1b
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mov r0,#0x20000
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bl __rb_delay*/
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MRC p15,0,r0,c1,c0,0
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BIC r0,r0,#(1<<0) @disable mmu
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BIC r0,r0,#(1<<13) @set vector to 0x00000000
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BIC r0,r0,#(1<<12) @disable I CACHE
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BIC r0,r0,#(1<<2) @disable D DACHE
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BIC r0,r0,#(1<<11) @disable Z
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BIC r0,r0,#(1<<28) @disable TRE
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MCR p15,0,r0,c1,c0,0
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MOV r0,#0
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mcr p15, 0, r0, c7, c10, 5
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mcr p15, 0, r0, c7, c10, 4
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isb
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dsb
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nop
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nop
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nop
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adr r7,__regs
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ldr r8,[r7,#0x10] @uart1 reg
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adr r3 , __dbg_info
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2:
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ldrb r1,[r3],#1
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cmp r1,#0
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strne r1,[r8,#0]
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bne 2b
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mov r0,#0x20000
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bl __rb_delay
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wait:
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@b wait
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@arm slow mod.
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ldr r8,[r7,#0xc] @CRU reg
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ldr r9,[r8,#0x10]
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bic r9,r9,#0x3 @CPU slow mode
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bic r9,r9,#(0x3<<2) @Peri slow mode
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str r9,[r8,#0]
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dsb
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mov r0,#0x10000
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bl __rb_delay
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@recover SPI clk
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ldr r9,[r8,#0x0c] @CRU_PPLL_CON bit 15=1, Peri PLL power down
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bic r9,r9,#(0x1<<15)
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str r9,[r8,#0x0c]
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dsb
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mov r0,#0x10000
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bl __rb_delay
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ldr r9,[r8,#0x2c] @CRU_CLKSEL6_CON bit [8:2] = 7, bit [1:0] =0
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bic r9,r9,#(0x7F<<2)
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bic r9,r9,#(0x3)
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orr r9,r9,#(0x7<<2)
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str r9,[r8,#0x2c]
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@recover eMMC clk
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ldr r9,[r8,#0x30] @CRU_CLKSEL7_CON bit [23:18] = 0x17, bit [1:0] = 0
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bic r9,r9,#(0x3F<<18)
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bic r9,r9,#0x3
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orr r9,r9,#(0x17<<18)
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str r9,[r8,#0x30]
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@recover UART1 clk
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ldr r9,[r8,#0x34] @CRU_CLKSEL8_CON bit [21:20] = 0x2, bit [19:14] = 0, bit [2:0] = 0
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bic r9,r9,#(0x3<<20)
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bic r9,r9,#(0x3F<<14)
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bic r9,r9,#0x7
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orr r9,r9,#(0x2<<20)
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str r9,[r8,#0x34]
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@clk enable
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ldr r9,[r8,#0x5c] @CRU_CLKGATE0_CON
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bic r9,r9,#(0x1<<31) @GRF clk enable
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bic r9,r9,#(0x1<<30) @PMU clk enable
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bic r9,r9,#(0x1<<27) @DEBUG clk enable
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bic r9,r9,#(0x7<<18) @DDR clk enable
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bic r9,r9,#(0x1<<14) @mask rom clk enable
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bic r9,r9,#(0x1<<12) @Int Mem clk enable
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bic r9,r9,#(0x1<<11) @GIC clk enable
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bic r9,r9,#(0xFF) @CPU clk enable
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bic r9,r9,#(0x1<<8)
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str r9,[r8,#0x5c]
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ldr r9,[r8,#0x60] @CRU_CLKGATE1_CON
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bic r9,r9,#(0x3<<25) @USB clk enable
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bic r9,r9,#(0x3<<23) @eMMC clk enable
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bic r9,r9,#(0x1<<16) @NANC clk enable
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bic r9,r9,#(0x1<<6) @DDR PERIPH AXI clk enable
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bic r9,r9,#0x17 @PERIPH clk enable
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str r9,[r8,#0x60]
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ldr r9,[r8,#0x64] @CRU_CLKGATE2_CON
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bic r9,r9,#(0x1<<26) @JTAG clk enable
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bic r9,r9,#(0x1<<15) @SPI0 clk enable
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bic r9,r9,#0x1 @UART1 clk enable
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str r9,[r8,#0x64]
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@soft de-reset
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ldr r9,[r8,#0x6c] @CRU_SOFTRST0_CON
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bic r9,r9,#(0x1<<25) @ARM core DEBUG soft de-reset
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bic r9,r9,#(0x1<<12) @mask rom soft de-reset
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bic r9,r9,#(0x1<<9) @Int Mem soft de-reset
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bic r9,r9,#(0x1<<8) @GIC soft de-reset
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bic r9,r9,#0x3F @CPU soft de-reset
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str r9,[r8,#0x6c]
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ldr r9,[r8,#0x70] @CRU_SOFTRST1_CON
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bic r9,r9,#(0x1<<28) @UART1 soft de-reset
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bic r9,r9,#(0x1<<25) @SPI0 soft de-reset
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bic r9,r9,#(0x7<<16) @USB0 soft de-reset
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bic r9,r9,#(0x1<<15) @EMMC soft de-reset
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bic r9,r9,#(0x1<<9) @NANC soft de-reset
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bic r9,r9,#0x3F @PERIPH soft de-reset
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str r9,[r8,#0x70]
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ldr r9,[r8,#0x74] @CRU_SOFTRST2_CON
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bic r9,r9,#(0x1F<<8) @DDR soft de-reset
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str r9,[r8,#0x74]
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@ unremap, and axi.
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ldr r8,[r7,#0] @GRF reg
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ldr r9,[r8,#0xc0]
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bic r9,r9,#(1<<21)
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str r9,[r8,#0xc0]
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mov r9,#0
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ldr r8,[r7,#4] @CPU_AXI_BUS0
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str r9,[r8,#0]
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ldr r8,[r7,#8] @AXI1
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str r9,[r8,#0]
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dsb
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@eMMC register recover
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ldr r8,[r7,#0] @GRF reg
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ldr r9,[r8,#0xbc] @GRF_SOC_CON0
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bic r9,r9,#(0x1<<9) @emmc_and_boot_en control=0
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str r9,[r8,#0xbc]
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ldr r8,[r7,#14] @eMMC reg
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mov r9,#0
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str r9,[r8,#0xc] @SDMMC_CLKSRC=0, clk_source=clock divider 0
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str r9,[r8,#0x18] @SDMMC_CTYPE=0, card_width=1 bit mode
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mov r9,#0x200
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str r9,[r8,#0x1c] @SDMMC_BLKSIZ=0x200, Block size=512
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ldr r8,[r7,#0x10] @uart1_reg
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adr r0 , __dbg_info1
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3:
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ldrb r1,[r0],#1
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cmp r1,#0
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strne r1,[r8,#0]
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bne 3b
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mov r0,#0x10000
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bl __rb_delay
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mov r4, #0
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mov pc, r4
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__prk:
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.long printk
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__rb_info:
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.asciz "at reboot function,pc=0x%x\n"
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__prk_info:
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.asciz "after printk!\n\r"
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__dbg_info:
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.asciz "AFTER DIS MMU\n\r"
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__dbg_info1:
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.asciz "LAST JUMP TO 0\n\r"
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.align
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__regs:
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.long RK29_GRF_PHYS @ 0x20008000 , unremap
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.long RK29_CPU_AXI_BUS0_PHYS @ 0x15000000
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.long RK29_AXI1_PHYS @ 0x10000000
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.long RK29_CRU_PHYS @ 0x20000000
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.long RK29_UART1_PHYS @ 0x20060000 , printk for debug.
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.long RK29_EMMC_PHYS @ 0x1021C000
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.align
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__rb_delay:
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subs r0, r0, #1
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bhi __rb_delay
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mov pc, lr
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#if FIQ_ENABLE
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.align
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ENTRY(rk28_fiq_handle)
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mrs r8, spsr
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adr r9,__fiq_save
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stmia r9 , {r0-r8,lr}
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mov r0,r9 @save addr.
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mov r5,#(SVC_MODE|PSR_I_BIT|PSR_F_BIT)
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msr cpsr_cxsf,r5 @ to svc mod.disable irq,fiq.
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sub r1, sp, #(S_FRAME_SIZE)
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add r2 , r1 , #32 @ r0--r7.
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stmia r2,{r8-lr} @ the svc sp not change here.
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ldmia r0,{r3-r10}
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stmia r1,{r3-r10}
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ldr r9,[r0,#36] @get fiq lr.
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sub r9,r9,#4
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str r9 , [r1,#S_PC]
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ldr r10,[r0,#32] @get fiq spsr.
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str r10, [r1,#S_PSR]
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mov r5,r1
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mov sp,r5 @stack frame
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mov r0,r5
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ldr r11,1f
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blx r11
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b 3f
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1:
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.long rk28_debug_fiq
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3:
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msr spsr_cxsf,r10
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ldmia r5, {r0 - pc}^
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__fiq_save: @for save fiq spsr r0-r7,spsr,lr.
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.long 0
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.previous
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#endif
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