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03e917b2a0
Tegra PMC has blink control to output 32 kHz clock out to Tegra blink pin. Blink pad DPD state and enable controls are part of Tegra PMC register space. Currently Tegra clock driver registers blink control by passing PMC address and register offset to clk_register_gate which performs direct PMC access during clk_ops and with this when PMC is in secure mode, any access from non-secure world does not go through. This patch adds blink control registration to the Tegra PMC driver using PMC specific clock gate operations that use tegra_pmc_readl() and tegra_pmc_writel() to support both secure mode and non-secure mode PMC register access. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.