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c92bd95324
commit 4c585af7180c147062c636a927a2fc2b6a7072f5 upstream Early microcode loading on 32-bit runs in physical address mode because the initrd is not covered by the initial page tables. That results in a horrible mess all over the microcode loader code. Provide a temporary mapping for the initrd in the initial page tables by appending it to the actual initial mapping starting with a new PGD or PMD depending on the configured page table levels ([non-]PAE). The page table entries are located after _brk_end so they are not permanently using memory space. The mapping is invalidated right away in i386_start_kernel() after the early microcode loader has run. This prepares for removing the physical address mode oddities from all over the microcode loader code, which in turn allows further cleanups. Provide the map and unmap code and document the place where the microcode loader needs to be invoked with a comment. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20231017211722.292291436@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MICROCODE_H
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#define _ASM_X86_MICROCODE_H
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struct cpu_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int rev;
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};
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struct ucode_cpu_info {
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struct cpu_signature cpu_sig;
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void *mc;
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};
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#ifdef CONFIG_MICROCODE
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void load_ucode_bsp(void);
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void load_ucode_ap(void);
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void microcode_bsp_resume(void);
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#else
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static inline void load_ucode_bsp(void) { }
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static inline void load_ucode_ap(void) { }
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static inline void microcode_bsp_resume(void) { }
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#endif
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extern unsigned long initrd_start_early;
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#ifdef CONFIG_CPU_SUP_INTEL
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/* Intel specific microcode defines. Public for IFS */
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struct microcode_header_intel {
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unsigned int hdrver;
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unsigned int rev;
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unsigned int date;
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unsigned int sig;
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unsigned int cksum;
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unsigned int ldrver;
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unsigned int pf;
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unsigned int datasize;
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unsigned int totalsize;
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unsigned int metasize;
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unsigned int reserved[2];
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};
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struct microcode_intel {
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struct microcode_header_intel hdr;
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unsigned int bits[];
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};
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#define DEFAULT_UCODE_DATASIZE (2000)
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#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
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#define MC_HEADER_TYPE_MICROCODE 1
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#define MC_HEADER_TYPE_IFS 2
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static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
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{
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return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
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}
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static inline u32 intel_get_microcode_revision(void)
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{
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u32 rev, dummy;
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native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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native_cpuid_eax(1);
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/* get the current revision from MSR 0x8B */
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native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
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return rev;
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}
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#endif /* !CONFIG_CPU_SUP_INTEL */
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bool microcode_nmi_handler(void);
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void microcode_offline_nmi_handler(void);
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#ifdef CONFIG_MICROCODE_LATE_LOADING
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DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
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static __always_inline bool microcode_nmi_handler_enabled(void)
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{
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return static_branch_unlikely(µcode_nmi_handler_enable);
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}
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#else
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static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
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#endif
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#endif /* _ASM_X86_MICROCODE_H */
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