Yash Shah 5545b6d1ba RISC-V: Add DT documentation for SiFive L2 Cache Controller ...

Add device tree bindings for SiFive FU540 L2 cache controller driver

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-05-16 20:42:13 -07:00

..

cpus.txt

dt-bindings: RISC-V CPU Bindings

2017-09-25 15:50:57 -07:00

sifive-l2-cache.txt

RISC-V: Add DT documentation for SiFive L2 Cache Controller

2019-05-16 20:42:13 -07:00