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a7cb2216f1
PD#166821: mm: reduce cache line size If cacheline size is set to 128, then smallest kmalloc is 128, this will cause low memory usage for slab and waste lot of memory. For ARM64, cacheline size is hardware set to 64 bytes. Reduce to 64 bytes can improve usage for slab. And can help to save memory. Change-Id: Id7f39bec324345d3e21f2a4e954803179fb54004 Signed-off-by: tao zeng <tao.zeng@amlogic.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#include <asm/cachetype.h>
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#ifdef CONFIG_AMLOGIC_MEMORY_EXTEND
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#define L1_CACHE_SHIFT 6
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#else
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#define L1_CACHE_SHIFT 7
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#endif /* CONFIG_AMLOGIC_MEMORY_EXTEND */
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#ifndef __ASSEMBLY__
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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static inline int cache_line_size(void)
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{
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u32 cwg = cache_type_cwg();
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return cwg ? 4 << cwg : L1_CACHE_BYTES;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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