Chen Zhong d6b6302c36 clk: mediatek: add the option for determining PLL source clock ...

[ Upstream commit c955bf3998 ]

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2017-12-20 10:07:29 +01:00

..

clk-apmixed.c

clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS

2015-10-01 12:06:00 +08:00

clk-gate.c

clk: mediatek: remove __init from clk registration functions

2016-08-18 17:15:30 -07:00

clk-gate.h

clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h

2016-01-29 12:59:50 -08:00

clk-mt8135.c

clk: mediatek: Properly include clk.h

2015-07-20 10:53:09 -07:00

clk-mt8173.c

clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap

2016-09-21 01:06:07 -07:00

clk-mtk.c

clk: mediatek: remove __init from clk registration functions

2016-08-18 17:15:30 -07:00

clk-mtk.h

clk: mediatek: add the option for determining PLL source clock

2017-12-20 10:07:29 +01:00

clk-pll.c

clk: mediatek: add the option for determining PLL source clock

2017-12-20 10:07:29 +01:00

Kconfig

clk: mediatek: Add hardware dependency

2016-10-17 15:22:26 -07:00

Makefile

clk: mediatek: Refine the makefile to support multiple clock drivers

2016-08-19 12:18:38 -07:00

reset.c

clk: mediatek: Make reset_control_ops const

2016-03-29 16:29:19 -07:00