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b829e96364
PD#SWPL-27008 Problem: exphy setting will del Solution: set delay once more Verify: verify on sm1 202 customer's board Change-Id: I47bb705bd13f17320f095589d1a08f89635b76b1 Signed-off-by: Zhuo Wang <zhuo.wang@amlogic.com>
364 lines
9.1 KiB
C
364 lines
9.1 KiB
C
/*
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* drivers/net/phy/realtek.c
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*
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* Driver for Realtek PHYs
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*
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* Author: Johnson Leung <r58129@freescale.com>
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/phy.h>
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#include <linux/module.h>
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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#include <linux/types.h>
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#include <linux/input.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/amlogic/pm.h>
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#endif
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#define RTL821x_LCR 0x10
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#define RTL821x_PHYSR 0x11
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#define RTL821x_PHYSR_DUPLEX 0x2000
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#define RTL821x_PHYSR_SPEED 0xc000
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#define RTL821x_INER 0x12
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#define RTL821x_INER_INIT 0x6400
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#define RTL821x_INSR 0x13
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#define RTL8211E_INER_LINK_STATUS 0x400
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#define RTL8211F_INER_LINK_STATUS 0x0010
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#define RTL8211F_INSR 0x1d
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#define RTL8211F_PAGE_SELECT 0x1f
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#define RTL8211F_TX_DELAY 0x100
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MODULE_DESCRIPTION("Realtek PHY driver");
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MODULE_AUTHOR("Johnson Leung");
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MODULE_LICENSE("GPL");
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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unsigned int support_external_phy_wol;
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unsigned int external_rx_delay;
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unsigned int external_tx_delay;
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#endif
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static int rtl821x_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, RTL821x_INSR);
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return (err < 0) ? err : 0;
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}
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static int rtl8211f_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43);
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err = phy_read(phydev, RTL8211F_INSR);
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/* restore to default page 0 */
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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return (err < 0) ? err : 0;
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}
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static int rtl8211b_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL821x_INER_INIT);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211e_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211E_INER_LINK_STATUS);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211f_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211F_INER_LINK_STATUS);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211f_config_init(struct phy_device *phydev)
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{
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int ret;
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u16 reg;
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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unsigned char *mac_addr = NULL;
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#endif
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ret = genphy_config_init(phydev);
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if (ret < 0)
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return ret;
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
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reg = phy_read(phydev, 0x11);
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/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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reg |= RTL8211F_TX_DELAY;
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else
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reg &= ~RTL8211F_TX_DELAY;
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phy_write(phydev, 0x11, reg);
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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/*switch page d08*/
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
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reg = phy_read(phydev, 0x15);
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if (external_rx_delay) {
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/*add 2ns delay for rx*/
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phy_write(phydev, 0x15, reg | 0x8);
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} else {
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/*del 2ns rx*/
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phy_write(phydev, 0x15, reg & 0xfff7);
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}
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if (external_tx_delay) {
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reg = phy_read(phydev, 0x11);
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phy_write(phydev, 0x11, reg | 0x100);
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}
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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/*disable clk_out pin 35 set page 0x0a43 reg25.0 as 0*/
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0a43);
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reg = phy_read(phydev, 0x19);
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/*set reg25 bit0 as 0*/
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reg = phy_write(phydev, 0x19, reg & 0xfffe);
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/* switch to page 0 */
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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/*reset phy to apply*/
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reg = phy_write(phydev, 0x0, 0x9200);
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/* config mac address for wol*/
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if ((phydev->attached_dev) && (support_external_phy_wol)) {
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mac_addr = phydev->attached_dev->dev_addr;
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd8c);
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phy_write(phydev, 0x10, mac_addr[0] | (mac_addr[1] << 8));
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phy_write(phydev, 0x11, mac_addr[2] | (mac_addr[3] << 8));
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phy_write(phydev, 0x12, mac_addr[4] | (mac_addr[5] << 8));
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} else {
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pr_debug("not set wol mac\n");
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}
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#endif
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd04); /*set page 0xd04*/
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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phy_write(phydev, RTL821x_LCR,
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(1 << 6) | (1 << 9) // LED1 - GREEN (100Mbps)
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| (1 << 13) | (1 << 14)); // LED2 - AMBER (1000Mbps)
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#else
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phy_write(phydev, RTL821x_LCR, 0XC171); /*led configuration*/
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#endif
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/* restore to default page 0 */
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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return 0;
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}
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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#include <linux/amlogic/scpi_protocol.h>
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static u32 enable_wol = 0;
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static int __init enable_wol_setup(char *str)
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{
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enable_wol = (str[0] != '0');
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support_external_phy_wol = enable_wol;
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return 0;
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}
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__setup("enable_wol=", enable_wol_setup);
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#endif
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int rtl8211f_suspend(struct phy_device *phydev)
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{
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int value = 0;
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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scpi_send_usr_data(SCPI_CL_WOL, &enable_wol, sizeof(enable_wol));
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#endif
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if (support_external_phy_wol) {
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mutex_lock(&phydev->lock);
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd8a);
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/*set magic packet for wol*/
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phy_write(phydev, 0x10, 0x1000);
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phy_write(phydev, 0x11, 0x9fff);
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/*pad isolation*/
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value = phy_read(phydev, 0x13);
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phy_write(phydev, 0x13, value | (0x1 << 15));
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/*pin 31 pull high*/
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd40);
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value = phy_read(phydev, 0x16);
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phy_write(phydev, 0x16, value | (1 << 5));
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0);
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mutex_unlock(&phydev->lock);
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} else {
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genphy_suspend(phydev);
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}
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return 0;
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}
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int rtl8211f_resume(struct phy_device *phydev)
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{
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int value;
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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u16 reg;
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/*switch page d08*/
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
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reg = phy_read(phydev, 0x15);
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if (external_rx_delay) {
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/*add 2ns delay for rx*/
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phy_write(phydev, 0x15, reg | 0x8);
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} else {
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/*del 2ns rx*/
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phy_write(phydev, 0x15, reg & 0xfff7);
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}
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if (external_tx_delay) {
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reg = phy_read(phydev, 0x11);
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phy_write(phydev, 0x11, reg | 0x100);
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} else {
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reg = phy_read(phydev, 0x11);
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reg &= ~RTL8211F_TX_DELAY;
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phy_write(phydev, 0x11, reg);
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}
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
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#endif
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if (support_external_phy_wol) {
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mutex_lock(&phydev->lock);
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd8a);
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phy_write(phydev, 0x10, 0x0);
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/*reset wol*/
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value = phy_read(phydev, 0x11);
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phy_write(phydev, 0x11, value & ~(0x1 << 15));
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/*pad isolantion*/
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value = phy_read(phydev, 0x13);
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phy_write(phydev, 0x13, value & ~(0x1 << 15));
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phy_write(phydev, RTL8211F_PAGE_SELECT, 0);
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mutex_unlock(&phydev->lock);
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} else {
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genphy_resume(phydev);
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}
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pr_debug("%s %d\n", __func__, __LINE__);
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return 0;
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}
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static void rtl8211f_remove(struct phy_device *phydev)
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{
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rtl8211f_suspend(phydev);
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}
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#endif
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static struct phy_driver realtek_drvs[] = {
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{
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.phy_id = 0x00008201,
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.name = "RTL8201CP Ethernet",
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.phy_id_mask = 0x0000ffff,
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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}, {
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.phy_id = 0x001cc912,
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.name = "RTL8211B Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211b_config_intr,
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}, {
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.phy_id = 0x001cc914,
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.name = "RTL8211DN Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = rtl821x_ack_interrupt,
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.config_intr = rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = 0x001cc915,
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.name = "RTL8211E Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = 0x001cc916,
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.name = "RTL8211F Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_aneg = &genphy_config_aneg,
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.config_init = &rtl8211f_config_init,
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.read_status = &genphy_read_status,
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.ack_interrupt = &rtl8211f_ack_interrupt,
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.config_intr = &rtl8211f_config_intr,
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#ifdef CONFIG_AMLOGIC_ETH_PRIVE
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.suspend = rtl8211f_suspend,
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.resume = rtl8211f_resume,
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.remove = rtl8211f_remove,
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#else
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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#endif
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},
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};
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module_phy_driver(realtek_drvs);
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static struct mdio_device_id __maybe_unused realtek_tbl[] = {
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{ 0x001cc912, 0x001fffff },
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{ 0x001cc914, 0x001fffff },
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{ 0x001cc915, 0x001fffff },
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{ 0x001cc916, 0x001fffff },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, realtek_tbl);
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