Shirish S a3ed353cf8 amdgpu/gmc_v9: save/restore sdpif regs during S3 ...

fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

2020-02-25 11:30:42 -05:00

..

dce_6_0_d.h

drm/amd/amdgpu: port of DCE v6 to new headers (v3)

2016-11-23 15:08:42 -05:00

dce_6_0_sh_mask.h

drm/amdgpu: add DP audio support for si dce6 (v3)

2017-05-24 17:39:58 -04:00

dce_8_0_d.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_8_0_enum.h

drm/amd: add dce8 enum register header

2016-02-10 14:17:02 -05:00

dce_8_0_sh_mask.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_10_0_d.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_10_0_enum.h

drm/amdgpu: add DCE 10.0 register headers

2015-06-03 21:02:53 -04:00

dce_10_0_sh_mask.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_11_0_d.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_11_0_enum.h

drm/amdgpu: add DCE 11.0 register headers

2015-06-03 21:02:54 -04:00

dce_11_0_sh_mask.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_11_2_d.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_11_2_enum.h

drm/amd: add DCE 11.2 register headers

2016-05-04 20:23:19 -04:00

dce_11_2_sh_mask.h

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

dce_12_0_offset.h

amdgpu/gmc_v9: save/restore sdpif regs during S3

2020-02-25 11:30:42 -05:00

dce_12_0_sh_mask.h

drm/amd: Add dce-12.1 gpio aux registers (v2)

2018-05-17 10:13:19 -05:00