Files
linux/arch/arm/mm
Huang, Tao 452b07f879 ARM: errata: Workaround for Cortex-A12 erratum 821420
On Cortex-A12 (r0p0, r0p1), in very rare timing conditions, a sequence of
VMOV to Core registers instructions, for which the second one is in the
shadow of a branch or abort, can lead to a deadlock when the VMOV
instructions are issued out-of-order. This workaround setting bit 1 of
the Internal Feature Register prevents the erratum.

Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2015-01-06 12:25:21 +08:00
..
2011-12-08 10:30:40 +00:00
2013-12-11 22:36:26 -08:00