Matt Roper 3a1b82a19f drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active ...

On gen12, we no longer need to disable DC5/DC6 when when PG2 is in use
(which translates to cases where we're using VDSC on pipe A).

Bspec: 49193
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220231843.3127468-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

2020-02-26 15:07:42 -08:00

..

drm

drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active

2020-02-26 15:07:42 -08:00

host1x

Merge tag 'drm/tegra/for-5.6-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next

2020-02-07 12:22:30 +10:00

ipu-v3

gpu: ipu-v3: image-convert: only sample into the next tile if necessary

2019-08-19 16:25:30 +02:00

vga

vga: Fix Kconfig indentation

2019-11-20 17:40:32 +01:00

Makefile

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