PD#SWPL-215
Problem:
1. additional or missing bytes be sent on mosi sometimes.
2. Customer DSP load firmware through SPICC. the loading time is 12s with
buildroot release 20180907 while 6s with 20180131.
3. rx error when work in loopback mode at high speed.
Solution:
1. change to disable irq at the irq-handle begining;
change to enable irq after all data pulled.
2. pre-setup of every spi transfer spends most of time on clk_set_rate().
this time is not obvious while cpu work at a high frequence such as
1000MHz.
In fact, a slave speed is almost fixed and we needn't set it for every
transfer but set only when speed changed.
3. disable auto io delay when in loopback mode.
Verify:
verified on axg-s400-v03 and tl1-skt
Change-Id: I61bcceccc243b218879b2b0711d0aff7538151f6
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
f9f6129703