Rex Zhu 4ccd2d931c drm/amd/pp: Implement force_clock_level for RV ...

under manual dpm mode, user can set gfx/mem clock
through sysfs pp_dpm_sclk/mclk on Rv.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2018-05-15 13:44:22 -05:00

..

drm

drm/amd/pp: Implement force_clock_level for RV

2018-05-15 13:44:22 -05:00

host1x

gpu: host1x: Use IOMMU groups

2017-12-21 14:52:36 +01:00

ipu-v3

gpu: ipu-v3: prg: avoid possible array underflow

2018-03-15 17:52:08 +01:00

vga

vga_switcheroo: Let HDA autosuspend on mux change

2018-03-13 22:58:49 +01:00

Makefile

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