Hai Li e01b1bfd88 drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY ...

The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

2015-10-22 15:39:54 -04:00

..

phy

drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY

2015-10-22 15:39:54 -04:00

pll

Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

2015-09-04 15:49:32 -07:00

dsi_cfg.c

drm/msm/dsi: Introduce DSI configuration module

2015-08-15 18:27:29 -04:00

dsi_cfg.h

drm/msm/dsi: Introduce DSI configuration module

2015-08-15 18:27:29 -04:00

dsi_host.c

drm: msm: dsi: Don't attempt changing voltage of switches

2015-10-22 15:39:53 -04:00

dsi_manager.c

drm/msm/dsi: Modify dsi manager bridge ops to work with external bridges

2015-08-15 18:27:26 -04:00

dsi.c

drm/msm/dsi: Allow dsi to connect to an external bridge

2015-08-15 18:27:25 -04:00

dsi.h

drm/msm/dsi: Return void from msm_dsi_phy_disable()

2015-08-15 18:27:28 -04:00

dsi.xml.h

drm/msm: update generated headers

2015-10-22 15:39:44 -04:00

mmss_cc.xml.h

drm/msm: update generated headers

2015-10-22 15:39:44 -04:00

sfpb.xml.h

drm/msm: update generated headers

2015-10-22 15:39:44 -04:00