Alexander Shiyan 70522827d6 gpu: ipu-v3: Fix i.MX51 CSI control registers offset ...

[ Upstream commit 2c0408dd0d ]

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.

Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2019-03-23 13:19:41 +01:00

..

drm

drm/sun4i: tcon: Prepare and enable TCON channel 0 clock at init

2019-03-13 14:04:59 -07:00

host1x

drm/tegra: dsi: Enhance runtime power management

2016-08-24 15:58:57 +02:00

ipu-v3

gpu: ipu-v3: Fix i.MX51 CSI control registers offset

2019-03-23 13:19:41 +01:00

vga

vgaarbiter: rst-ifiy and polish kerneldoc

2016-08-16 18:49:56 +02:00

Makefile

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