mirror of
https://github.com/hardkernel/linux.git
synced 2026-04-10 23:18:10 +09:00
9274f2a4fc
This reverts commit 9730348075.
All Rockchip SoCs only have 64 bytes cache line length, so
it is not need this patch, which increase memory consumption.
Change-Id: Idf684189e7f7011562337a70dc7d26c8dceee7a6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#ifndef __ASM_CACHE_H
|
|
#define __ASM_CACHE_H
|
|
|
|
#include <asm/cachetype.h>
|
|
|
|
#define L1_CACHE_SHIFT 6
|
|
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
|
|
|
/*
|
|
* Memory returned by kmalloc() may be used for DMA, so we must make
|
|
* sure that all such allocations are cache aligned. Otherwise,
|
|
* unrelated code may cause parts of the buffer to be read into the
|
|
* cache before the transfer is done, causing old data to be seen by
|
|
* the CPU.
|
|
*/
|
|
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
|
|
|
static inline int cache_line_size(void)
|
|
{
|
|
u32 cwg = cache_type_cwg();
|
|
return cwg ? 4 << cwg : L1_CACHE_BYTES;
|
|
}
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif
|