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b1da356f4a
On some MIPS systems, a subset of devices may have DMA coherent with CPU
caches. For example in systems including a MIPS I/O Coherence Unit
(IOCU), some devices may be connected to that IOCU whilst others are
not.
Prior to this patch, we have a plat_device_is_coherent() function but no
implementation which does anything besides return a global true or
false, optionally chosen at runtime. For devices such as those described
above this is insufficient.
Fix this by tracking DMA coherence on a per-device basis with a
dma_coherent field in struct dev_archdata. Setting this from
arch_setup_dma_ops() takes care of devices which set the dma-coherent
property via device tree, and any PCI devices beneath a bridge described
in DT, automatically.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14349/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 20d330645c)
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
25 lines
436 B
C
25 lines
436 B
C
/*
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* Arch specific extensions to struct device
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*
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* This file is released under the GPLv2
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*/
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#ifndef _ASM_MIPS_DEVICE_H
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#define _ASM_MIPS_DEVICE_H
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struct dma_map_ops;
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struct dev_archdata {
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/* DMA operations on that device */
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struct dma_map_ops *dma_ops;
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#ifdef CONFIG_DMA_PERDEV_COHERENT
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/* Non-zero if DMA is coherent with CPU caches */
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bool dma_coherent;
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#endif
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};
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struct pdev_archdata {
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};
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#endif /* _ASM_MIPS_DEVICE_H*/
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