Andy Shevchenko 34c1b03029 dmaengine: hsu: correct use of channel status register ...

commit 4f4bc0abff upstream.

There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.

Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.

Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.

Fixes: 2b49e0c567 ("dmaengine: append hsu DMA driver")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2016-05-04 14:48:42 -07:00

..

hsu.c

dmaengine: hsu: correct use of channel status register

2016-05-04 14:48:42 -07:00

hsu.h

dmaengine: hsu: correct use of channel status register

2016-05-04 14:48:42 -07:00

Kconfig

dmaengine: hsu: make the UART driver in control of selecting this driver

2015-10-17 21:22:08 -07:00

Makefile

dmaengine: append hsu DMA driver

2015-03-07 03:23:02 +01:00

pci.c

dmaengine: hsu: remove platform data

2015-10-17 21:22:08 -07:00