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f9eefeeaa7
Change-Id: I754250669891307b0deab2bdab1bd01512713f79 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_H
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#define _DT_BINDINGS_CLOCK_ROCKCHIP_H
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#define CLK_DIVIDER_PLUS_ONE (0)
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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/* Rockchip special defined */
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//#define CLK_DIVIDER_FIXED BIT(6)
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#define CLK_DIVIDER_USER_DEFINE BIT(7)
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/*
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* flags used across common struct clk. these flags should only affect the
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* top-level framework. custom flags for dealing with hardware specifics
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* belong in struct clk_foo
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*/
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent
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and set_div on rate change */
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/* Rockchip pll flags */
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#define CLK_PLL_3188 BIT(0)
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#define CLK_PLL_3188_APLL BIT(1)
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#define CLK_PLL_3188PLUS BIT(2)
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#define CLK_PLL_3188PLUS_APLL BIT(3)
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#define CLK_PLL_3288_APLL BIT(4)
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#define CLK_PLL_3188PLUS_AUTO BIT(5)
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#define CLK_PLL_3036_APLL BIT(6)
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#define CLK_PLL_3036PLUS_AUTO BIT(7)
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#define CLK_PLL_312XPLUS BIT(8)
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#define CLK_PLL_3368_APLLB BIT(9)
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#define CLK_PLL_3368_APLLL BIT(10)
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#define CLK_PLL_3368_LOW_JITTER BIT(11)
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/* rate_ops index */
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#define CLKOPS_RATE_MUX_DIV 1
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#define CLKOPS_RATE_EVENDIV 2
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#define CLKOPS_RATE_MUX_EVENDIV 3
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#define CLKOPS_RATE_I2S_FRAC 4
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#define CLKOPS_RATE_FRAC 5
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#define CLKOPS_RATE_I2S 6
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#define CLKOPS_RATE_CIFOUT 7
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#define CLKOPS_RATE_UART 8
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#define CLKOPS_RATE_HSADC 9
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#define CLKOPS_RATE_MAC_REF 10
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#define CLKOPS_RATE_CORE 11
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#define CLKOPS_RATE_CORE_CHILD 12
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#define CLKOPS_RATE_DDR 13
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#define CLKOPS_RATE_RK3288_I2S 14
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#define CLKOPS_RATE_RK3288_USB480M 15
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#define CLKOPS_RATE_RK3288_DCLK_LCDC0 16
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#define CLKOPS_RATE_RK3288_DCLK_LCDC1 17
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#define CLKOPS_RATE_DDR_DIV2 18
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#define CLKOPS_RATE_DDR_DIV4 19
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#define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20
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#define CLKOPS_RATE_RK3368_DCLK_LCDC 21
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#define CLKOPS_RATE_RK3368_DDR 22
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#define CLKOPS_TABLE_END (~0)
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/* pd id */
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#define CLK_PD_BCPU 0
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#define CLK_PD_BDSP 1
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#define CLK_PD_BUS 2
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#define CLK_PD_CPU_0 3
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#define CLK_PD_CPU_1 4
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#define CLK_PD_CPU_2 5
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#define CLK_PD_CPU_3 6
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#define CLK_PD_CS 7
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#define CLK_PD_GPU 8
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#define CLK_PD_HEVC 9
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#define CLK_PD_PERI 10
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#define CLK_PD_SCU 11
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#define CLK_PD_VIDEO 12
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#define CLK_PD_VIO 13
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#define CLK_PD_GPU_0 14
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#define CLK_PD_GPU_1 15
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#define CLK_PD_VIRT 255
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/* reset flag */
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#define ROCKCHIP_RESET_HIWORD_MASK BIT(0)
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#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */
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