Vijay Purushothaman 74a4dd2e45 drm/i915: Program correct m n tu register for Valleyview ...

m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2012-09-28 16:49:53 +02:00

..

drm

drm/i915: Program correct m n tu register for Valleyview

2012-09-28 16:49:53 +02:00

stub

i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO

2011-04-13 09:10:25 +10:00

vga

vga_switcheroo: Don't require handler init callback

2012-08-17 17:34:41 -04:00

Makefile

gpu: Add Intel GMA500(Poulsbo) Stub Driver

2010-10-26 11:00:13 +10:00