Files
linux/arch/xtensa/kernel
Max Filippov 596121c889 xtensa: add missing isync to the cpu_reset TLB code
commit cd8869f4cb upstream.

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-05-15 14:18:19 +09:00
..
2017-06-17 06:41:58 +02:00
2023-05-15 12:22:50 +09:00
2023-05-15 11:50:19 +09:00