Chen-Yu Tsai 7e81bda23a drm/sun4i: dotclock: Allow divider = 127 ...

The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.

Make the end condition of the for loop inclusive of 127 in the
round_rate callback.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

2016-09-18 21:13:35 +02:00

..

drm

drm/sun4i: dotclock: Allow divider = 127

2016-09-18 21:13:35 +02:00

host1x

gpu: host1x: Remove useless local variable

2016-06-23 11:59:33 +02:00

ipu-v3

gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_format

2016-07-12 18:26:05 +02:00

vga

vga_switcheroo: Sphinxify docs

2016-07-12 16:14:36 +02:00

Makefile

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00