Zheng Yang 064184ce17 drm/rockchip: dw-hdmi: fix 3328/3228 phy bus width ...

If HDMI output corlor mode is YCbCr422, the tmds clock is same
to YCbCr444 8bit, phy bus width should be set to 8.

Change-Id: I6e844e676a6315ae0cb88b0bd8456f0e27fa5e0c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

2017-12-27 16:34:05 +08:00

..

arm

MALI Utgard: RK: only prepare clk_gpu not enable it in mali_probe()

2017-12-11 18:49:22 +08:00

drm

drm/rockchip: dw-hdmi: fix 3328/3228 phy bus width

2017-12-27 16:34:05 +08:00

host1x

rk: revert to v3.10

2015-11-11 15:57:28 +08:00

ipu-v3

drm/imx: Match imx-ipuv3-crtc components using device node in platform data

2016-06-07 18:14:37 -07:00

rogue

RK3368 GPU version: Rogue L 0.22

2015-08-17 14:12:00 +08:00

rogue_m

GPU: Rogue_M: update to 1.31_2 version & support gpu pd.

2016-01-18 19:04:28 +08:00

vga

vgaarb: fix signal handling in vga_get()

2015-12-11 14:04:44 +10:00

Makefile

MALI: add midgard src dir

2016-03-09 16:51:03 +08:00