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commit5686a1e5aaupstream. Until now, the mvebu-mbus was guessing by itself whether hardware I/O coherency was available or not by poking into the Device Tree to see if the coherency fabric Device Tree node was present or not. However, on some upcoming SoCs, the presence or absence of the coherency fabric DT node isn't sufficient: in CONFIG_SMP, the coherency can be enabled, but not in !CONFIG_SMP. In order to clean this up, the mvebu_mbus_dt_init() function is extended to get a boolean argument telling whether coherency is enabled or not. Therefore, the logic to decide whether coherency is available or not now belongs to the core SoC code instead of the mvebu-mbus driver itself, which is much better. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> [ Greg Ungerer: back ported to linux-3.10.y Back port necessary due to large code differences in affected files. This change in combination with commite553554536("ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP") is critical to the hardware I/O coherency being set correctly by both the mbus driver and all peripheral hardware drivers. Without this change drivers will incorrectly enable I/O coherency window attributes and this causes rare unreliable system behavior including oops. ] Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
/*
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* Marvell MBUS common definitions.
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*
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* Copyright (C) 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __LINUX_MBUS_H
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#define __LINUX_MBUS_H
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struct mbus_dram_target_info
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{
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/*
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* The 4-bit MBUS target ID of the DRAM controller.
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*/
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u8 mbus_dram_target_id;
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/*
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* The base address, size, and MBUS attribute ID for each
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* of the possible DRAM chip selects. Peripherals are
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* required to support at least 4 decode windows.
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*/
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int num_cs;
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struct mbus_dram_window {
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u8 cs_index;
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u8 mbus_attr;
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u32 base;
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u32 size;
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} cs[4];
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};
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/* Flags for PCI/PCIe address decoding regions */
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#define MVEBU_MBUS_PCI_IO 0x1
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#define MVEBU_MBUS_PCI_MEM 0x2
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#define MVEBU_MBUS_PCI_WA 0x3
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/*
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* Magic value that explicits that we don't need a remapping-capable
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* address decoding window.
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*/
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#define MVEBU_MBUS_NO_REMAP (0xffffffff)
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/* Maximum size of a mbus window name */
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#define MVEBU_MBUS_MAX_WINNAME_SZ 32
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/*
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* The Marvell mbus is to be found only on SOCs from the Orion family
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* at the moment. Provide a dummy stub for other architectures.
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*/
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#ifdef CONFIG_PLAT_ORION
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extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
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#else
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static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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return NULL;
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}
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#endif
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int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
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size_t size, phys_addr_t remap,
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unsigned int flags);
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int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
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size_t size);
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int mvebu_mbus_del_window(phys_addr_t base, size_t size);
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int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
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size_t mbus_size, phys_addr_t sdram_phys_base,
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size_t sdram_size, int is_coherent);
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#endif /* __LINUX_MBUS_H */
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