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[ Upstream commit 6da24ba932082bae110feb917a64bb54637fa7c0 ] With the standard Qualcomm TrustZone setup, components such as lpasscc, pdc_reset and watchdog shouldn't be touched by Linux. Mark them with the status 'reserved' and reenable them in the chrome-common dtsi. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-1-14bb7cedadf5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> Stable-dep-of: 6897fac411db ("arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered") Signed-off-by: Sasha Levin <sashal@kernel.org>
127 lines
2.4 KiB
Plaintext
127 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sc7280 fragment for devices with Chrome bootloader
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*
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* This file mainly tries to abstract out the memory protections put into
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* place by the Chrome bootloader which are different than what's put into
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* place by Qualcomm's typical bootloader. It also has a smattering of other
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* things that will hold true for any conceivable Chrome design
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*
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* Copyright 2022 Google LLC.
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*/
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/*
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* Reserved memory changes
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*
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* Delete all unused memory nodes and define the peripheral memory regions
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* required by the setup for Chrome boards.
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*/
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/delete-node/ &hyp_mem;
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/delete-node/ &xbl_mem;
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/delete-node/ &reserved_xbl_uefi_log;
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/delete-node/ &sec_apps_mem;
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/ {
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reserved-memory {
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adsp_mem: memory@86700000 {
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reg = <0x0 0x86700000 0x0 0x2800000>;
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no-map;
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};
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camera_mem: memory@8ad00000 {
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reg = <0x0 0x8ad00000 0x0 0x500000>;
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no-map;
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};
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venus_mem: memory@8b200000 {
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reg = <0x0 0x8b200000 0x0 0x500000>;
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no-map;
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};
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mpss_mem: memory@8b800000 {
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reg = <0x0 0x8b800000 0x0 0xf600000>;
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no-map;
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};
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wpss_mem: memory@9ae00000 {
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reg = <0x0 0x9ae00000 0x0 0x1900000>;
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no-map;
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};
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mba_mem: memory@9c700000 {
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reg = <0x0 0x9c700000 0x0 0x200000>;
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no-map;
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};
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};
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};
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&lpass_aon {
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status = "okay";
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};
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&lpass_core {
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status = "okay";
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};
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&lpass_hm {
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status = "okay";
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};
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&lpasscc {
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status = "okay";
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};
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&pdc_reset {
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status = "okay";
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};
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/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
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&pmk8350_pon {
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status = "disabled";
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};
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/*
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* Chrome designs always boot from SPI flash hooked up to the qspi.
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*
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* It's expected that all boards will support "dual SPI" at 37.5 MHz.
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* If some boards need a different speed or have a package that allows
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* Quad SPI together with WP then those boards can easily override.
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*/
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&qspi {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
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spi_flash: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <37500000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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&remoteproc_wpss {
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status = "okay";
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firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
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};
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/* Increase the size from 2.5MB to 8MB */
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&rmtfs_mem {
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reg = <0x0 0x9c900000 0x0 0x800000>;
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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wifi-firmware {
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iommus = <&apps_smmu 0x1c02 0x1>;
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};
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};
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