Jim Harris 3a46101871 cxl/region: fix x9 interleave typo ...

[ Upstream commit c7ad3dc3649730af483ee1e78be5d0362da25bfe ]

CXL supports x3, x6 and x12 - not x9.

Fixes: 80d10a6cee ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link: https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2024-01-25 15:27:48 -08:00

..

core

cxl/region: fix x9 interleave typo

2024-01-25 15:27:48 -08:00

acpi.c

cxl: Unify debug messages when calling devm_cxl_add_port()

2023-11-28 17:07:17 +00:00

cxl.h

tools/testing/cxl: Define a fixed volatile configuration to parse

2023-11-28 17:07:17 +00:00

cxlmem.h

tools/testing/cxl: Define a fixed volatile configuration to parse

2023-11-28 17:07:17 +00:00

cxlpci.h

cxl: Wait Memory_Info_Valid before access memory related info

2023-05-30 14:03:32 +01:00

Kconfig

cxl/region: Allocate HPA capacity to regions

2022-07-25 12:18:06 -07:00

Makefile

PM: CXL: Disable suspend

2022-04-22 16:09:42 -07:00

mem.c

cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem

2023-11-28 17:07:17 +00:00

pci.c

cxl/pci: Create PCI DOE mailbox's for memory devices

2022-07-19 15:38:04 -07:00

pmem.c

cxl/pmem: Fix nvdimm registration races

2023-03-10 09:34:20 +01:00

port.c

cxl/port: Read CDAT table

2022-07-19 15:38:05 -07:00