Masahiro Yamada c488c2e141 clk: uniphier: fix DAPLL2 clock rate of Pro5 ...

[ Upstream commit 67affb78a4 ]

The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2017-12-14 09:28:24 +01:00

..

clk-uniphier-core.c

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs

2016-10-19 13:15:05 -07:00

clk-uniphier-fixed-factor.c

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clk-uniphier-fixed-rate.c

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clk-uniphier-gate.c

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clk-uniphier-mio.c

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs

2016-10-19 13:15:05 -07:00

clk-uniphier-mux.c

clk: uniphier: fix type of variable passed to regmap_read()

2016-10-17 15:20:52 -07:00

clk-uniphier-peri.c

clk: uniphier: add clock data for UniPhier SoCs

2016-09-16 16:31:38 -07:00

clk-uniphier-sys.c

clk: uniphier: fix DAPLL2 clock rate of Pro5

2017-12-14 09:28:24 +01:00

clk-uniphier.h

clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs

2016-10-19 13:15:05 -07:00

Kconfig

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Makefile

clk: uniphier: add clock data for UniPhier SoCs

2016-09-16 16:31:38 -07:00