f78d982959
Change-Id: I8691f53540d566d00945fe3c7b6fb2f5f317cc1f Signed-off-by: Steve Jeong <jkhpro1003@gmail.com>
105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/*----------------------------------------------------------------------------*/
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/*
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WiringPi ODROID-M1 Board Header file
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*/
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/*----------------------------------------------------------------------------*/
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/*******************************************************************************
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Copyright (C) 2021 steve Jeong <jkhpro1003@gmail.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*******************************************************************************/
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#ifndef __ODROID_M1_H__
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#define __ODROID_M1_H__
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#define WIRINGPI 0
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#define LIBGPIOD 1
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/*----------------------------------------------------------------------------*/
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// Common mmap block size for ODROID-M1 GRF register
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#define M1_GPIO_PIN_BASE 0
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//setClkState mode
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#define M1_CLK_ENABLE 0
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#define M1_CLK_DISABLE 1
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#define M1_CLK_BYTE_ENABLE 2
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#define M1_CLK_BYTE_DISABLE 3
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#define M1_GRF_BLOCK_SIZE 0xFFFF
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#define GPIO_SIZE 32
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#define M1_FUNC_GPIO 0
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// GPIO[0]
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#define M1_GPIO_0_BASE 0xFDD60000
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// to control clock (PMU_CRU)
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#define M1_PMU_CRU_BASE 0xFDD00000
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#define M1_PMU_CRU_GPIO_CLK_OFFSET 0x0184
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#define M1_PMU_CRU_GPIO_PCLK_BIT 9
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// to control IOMUX
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#define M1_PMU_GRF_BASE 0xFDC20000
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#define M1_PMU_GRF_IOMUX_OFFSET 0x0000
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#define M1_PMU_GRF_PUPD_OFFSET 0x0020
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#define M1_PMU_GRF_DS_OFFSET 0x0070
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// GPIO[1:4]
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#define M1_GPIO_1_BASE 0xFE740000
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#define M1_GPIO_2_BASE 0xFE750000
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#define M1_GPIO_3_BASE 0xFE760000
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#define M1_GPIO_4_BASE 0xFE770000
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// to control clock (SYS_CRU)
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#define M1_CRU_BASE 0xFDD20000
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#define M1_CRU_GPIO_CLK_OFFSET 0x037C
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#define M1_CRU_GPIO_PCLK_BIT 2
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// to control IOMUX
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#define M1_SYS_GRF_BASE 0xFDC60000
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#define M1_SYS_GRF_IOMUX_OFFSET 0x0000
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#define M1_SYS_GRF_PUPD_OFFSET 0x0080
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#define M1_SYS_GRF_DS_OFFSET 0x0200
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// Common offset for GPIO registers from each GPIO bank's base address
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#define M1_GPIO_DIR_OFFSET 0x0008
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#define M1_GPIO_SET_OFFSET 0x0000
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#define M1_GPIO_GET_OFFSET 0x0070
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// GPIO DS LEVELS
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#define DS_LEVEL_0 0x01 //0b000001
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#define DS_LEVEL_1 0x03 //0b000011
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#define DS_LEVEL_2 0x07 //0b000111
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#define DS_LEVEL_3 0x0f //0b001111
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#define DS_LEVEL_4 0x1f //0b011111
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#define DS_LEVEL_5 0x3f //0b111111
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//GPIO write mask for WriteByte
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#define WRITE_BYTE_MASK_GPIO0_H 0x00030000
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#define WRITE_BYTE_MASK_GPIO0_L 0x40000000
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#define WRITE_BYTE_MASK_GPIO3_H 0x03C00000
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#define WRITE_BYTE_MASK_GPIO3_L 0x04000000
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#define CONSUMER "consumer"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void init_odroidm1 (struct libodroid *libwiring);
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#ifdef __cplusplus
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}
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#endif
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/*----------------------------------------------------------------------------*/
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#endif /* __ODROID_M1_H__ */
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/*----------------------------------------------------------------------------*/
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