amvecm: ai pq no scene change [1/1]

PD#SWPL-150247

Problem:
cm hist no update.

Solution:
modify code flow for cm hist update.

Verify:
t3x

Change-Id: I2a4260e98dc249b60040ab914cd9a2e941c58806
Signed-off-by: qinghui.jiang <qinghui.jiang@amlogic.com>

drivers/media/enhancement/amvecm/ai_pq/ai_pq.c

@@ -29,6 +29,7 @@
 #include "../dnlp_cal.h"
 #include "../cm2_adj.h"
 #include "../reg_helper.h"
+#include "../amve.h"
 
 unsigned int aipq_debug;
 module_param(aipq_debug, uint, 0664);
@@ -356,12 +357,8 @@ int peaking_scene_process(int offset, int enable)
 	adap_param->satur_param.offset = offset;
 
 	if (!enable || !(aipq_en & (1 << PEAKING_SCENE))) {
-		VSYNC_WRITE_VPP_REG_BITS(SRSHARP0_PK_FINALGAIN_HP_BP,
-			base_val[0] << 8 | base_val[1],
-			0, 16);
-		VSYNC_WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP,
-			base_val[2] << 8 | base_val[3],
-			0, 16);
+		set_sharpness_gain(base_val[0] << 8 | base_val[1],
+			base_val[2] << 8 | base_val[3]);
 		first_frame = 1;
 		return 0;
 	}
@@ -424,12 +421,8 @@ int peaking_scene_process(int offset, int enable)
 		}
 	}
 
-	VSYNC_WRITE_VPP_REG_BITS(SRSHARP0_PK_FINALGAIN_HP_BP,
-				 reg_val[0] << 8 | reg_val[1],
-				 0, 16);
-	VSYNC_WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP,
-				 reg_val[2] << 8 | reg_val[3],
-				 0, 16);
+	set_sharpness_gain(reg_val[0] << 8 | reg_val[1],
+		reg_val[2] << 8 | reg_val[3]);
 
 	return 0;
 }

drivers/media/enhancement/amvecm/amcm.c

@@ -870,6 +870,7 @@ void cm_frame_size_s5(struct vframe_s *vf, int vpp_index)
 	int i;
 	int changed_flag;
 	int slice_max;
+	int overlap = 0;
 
 #if CONFIG_AMLOGIC_MEDIA_VIDEO
 	vd_size_info = get_vd_proc_amvecm_info();
@@ -939,8 +940,13 @@ void cm_frame_size_s5(struct vframe_s *vf, int vpp_index)
 
 			for (i = SLICE0; i < slice_num; i++) {
 #if CONFIG_AMLOGIC_MEDIA_VIDEO
-				width = vd_size_info->slice[i].hsize;
-				height = vd_size_info->slice[i].vsize;
+				if (slice_num == 2)
+					overlap = vd_size_info->slice[0].vd1_overlap;
+				else
+					overlap = 0;
+
+				width = vd_size_info->slice[0].vd1_slice_in_hsize - overlap;
+				height = vd_size_info->slice[0].vd1_slice_in_vsize;
 #else
 				width = 0xf00;
 				height = 0x870;

drivers/media/enhancement/amvecm/amve.c

@@ -236,6 +236,9 @@ static unsigned int sr_adapt_level;
 module_param(sr_adapt_level, uint, 0664);
 MODULE_PARM_DESC(sr_adapt_level, "\n sr_adapt_level\n");
 
+/*sharpness gain for ai pq*/
+int sr_gain[2];
+
 /* *********************************************************************** */
 /* *** VPP_FIQ-oriented functions **************************************** */
 /* *********************************************************************** */
@@ -3027,6 +3030,31 @@ void vpp_pst_hist_sta_read(unsigned int *hist)
 	for (i = 0; i < 64; i++)
 		hist[i] = READ_VPP_REG(VPP_PST_STA_RO_HIST);
 }
+
+void set_sharpness_gain(int sr0_gain, int sr1_gain)
+{
+	sr_gain[0] = sr0_gain;
+	sr_gain[1] = sr1_gain;
+
+	vecm_latch_flag2 |= SHARPNESS_GAIN_UPDATE;
+}
+
+void sharpness_gain_update(int vpp_index)
+{
+	if (vecm_latch_flag2 & SHARPNESS_GAIN_UPDATE) {
+		if (chip_type_id != chip_t3x) {
+			VSYNC_WRITE_VPP_REG_BITS(SRSHARP0_PK_FINALGAIN_HP_BP,
+				sr_gain[0], 0, 16);
+			VSYNC_WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP,
+				sr_gain[0], 0, 16);
+		} else {
+			ve_sharpness_gain_set(sr_gain[0], sr_gain[1],
+				WR_DMA, vpp_index);
+		}
+
+		vecm_latch_flag2 &= ~SHARPNESS_GAIN_UPDATE;
+	}
+}
 #endif
 
 void amvecm_wb_enable(int enable)

drivers/media/enhancement/amvecm/amve.h

@@ -231,5 +231,7 @@ void set_vpp_enh_clk(struct vframe_s *vf, struct vframe_s *rpt_vf, int vpp_index
 void lut3d_update(unsigned int p3dlut_in[][3], int vpp_index);
 
 extern int dnlp_en_dsw;
+void set_sharpness_gain(int sr0_gain, int sr1_gain);
+void sharpness_gain_update(int vpp_index);
 #endif
 

drivers/media/enhancement/amvecm/amve_v2.c

@@ -602,38 +602,50 @@ void cm_hist_get(struct vframe_s *vf,
 {
 	int i;
 	struct cm_port_s port;
+	unsigned int reg_addr_s0;
+	unsigned int reg_addr_s1;
+	unsigned int reg_data_s0;
+	unsigned int reg_data_s1;
+	unsigned int val_s0 = 0;
+	unsigned int val_s1 = 0;
+	int slice_case;
 
 	if (!vf || !hue_bin0 || !sat_bin0)
 		return;
 
-	if (hist_dma_case && chip_type_id > chip_t3x) {
-		if (ve_multi_slice_case_get()) {
-			am_dma_get_blend_cm2_hist_hue(vf->prop.hist.vpp_hue_gamma,
-				32);
-			am_dma_get_blend_cm2_hist_sat(vf->prop.hist.vpp_sat_gamma,
-				32);
-		} else {
-			am_dma_get_mif_data_cm2_hist_hue(0,
-				vf->prop.hist.vpp_hue_gamma, 32);
-			am_dma_get_mif_data_cm2_hist_sat(0,
-				vf->prop.hist.vpp_sat_gamma, 32);
-		}
-	} else {
-		port = get_cm_port();
+	slice_case = ve_multi_slice_case_get();
 
-		for (i = 0; i < 32; i++) {
-			WRITE_VPP_REG(port.cm_addr_port[0],
-				hue_bin0 + i);
-			vf->prop.hist.vpp_hue_gamma[i] =
-				READ_VPP_REG(port.cm_data_port[0]);
+	port = get_cm_port();
+	reg_addr_s0 = port.cm_addr_port[0];
+	reg_addr_s1 = port.cm_addr_port[1];
+	reg_data_s0 = port.cm_data_port[0];
+	reg_data_s1 = port.cm_data_port[1];
+
+	for (i = 0; i < 32; i++) {
+		WRITE_VPP_REG(reg_addr_s0, hue_bin0 + i);
+		val_s0 = READ_VPP_REG(reg_data_s0);
+
+		if (chip_type_id == chip_t3x && slice_case) {
+			WRITE_VPP_REG(reg_addr_s1, hue_bin0 + i);
+			val_s1 = READ_VPP_REG(reg_data_s1);
 		}
 
-		for (i = 0; i < 32; i++) {
-			WRITE_VPP_REG(port.cm_addr_port[0],
-				sat_bin0 + i);
-			vf->prop.hist.vpp_sat_gamma[i] =
-				READ_VPP_REG(port.cm_data_port[0]);
+		vf->prop.hist.vpp_hue_gamma[i] = val_s0 + val_s1;
+	}
+
+	val_s0 = 0;
+	val_s1 = 0;
+
+	for (i = 0; i < 32; i++) {
+		WRITE_VPP_REG(reg_addr_s0, sat_bin0 + i);
+		val_s0 = READ_VPP_REG(reg_data_s0);
+
+		if (chip_type_id == chip_t3x && slice_case) {
+			WRITE_VPP_REG(reg_addr_s1, sat_bin0 + i);
+			val_s1 = READ_VPP_REG(reg_data_s1);
 		}
+
+		vf->prop.hist.vpp_sat_gamma[i] = val_s0 + val_s1;
 	}
 }
 
@@ -643,31 +655,35 @@ void cm_hist_by_type_get(enum cm_hist_e hist_sel,
 {
 	int i;
 	struct cm_port_s port;
+	unsigned int reg_addr_s0;
+	unsigned int reg_addr_s1;
+	unsigned int reg_data_s0;
+	unsigned int reg_data_s1;
+	unsigned int val_s0 = 0;
+	unsigned int val_s1 = 0;
+	int slice_case;
 
 	if (!data || !length || !addr_bin0)
 		return;
 
-	if (hist_dma_case) {
-		if (ve_multi_slice_case_get()) {
-			if (hist_sel == CM_HUE_HIST)
-				am_dma_get_blend_cm2_hist_hue(data, length);
-			else
-				am_dma_get_blend_cm2_hist_sat(data, length);
-		} else {
-			if (hist_sel == CM_HUE_HIST)
-				am_dma_get_mif_data_cm2_hist_hue(0, data, length);
-			else
-				am_dma_get_mif_data_cm2_hist_sat(0, data, length);
-		}
-	} else {
-		port = get_cm_port();
+	slice_case = ve_multi_slice_case_get();
 
-		for (i = 0; i < length; i++) {
-			WRITE_VPP_REG(port.cm_addr_port[0],
-				addr_bin0 + i);
-			data[i] =
-				READ_VPP_REG(port.cm_data_port[0]);
+	port = get_cm_port();
+	reg_addr_s0 = port.cm_addr_port[0];
+	reg_addr_s1 = port.cm_addr_port[1];
+	reg_data_s0 = port.cm_data_port[0];
+	reg_data_s1 = port.cm_data_port[1];
+
+	for (i = 0; i < length; i++) {
+		WRITE_VPP_REG(reg_addr_s0, addr_bin0 + i);
+		val_s0 = READ_VPP_REG(reg_data_s0);
+
+		if (chip_type_id == chip_t3x && slice_case) {
+			WRITE_VPP_REG(reg_addr_s1, addr_bin0 + i);
+			val_s1 = READ_VPP_REG(reg_data_s1);
 		}
+
+		data[i] = val_s0 + val_s1;
 	}
 }
 
@@ -1572,6 +1588,44 @@ void ve_mtrx_setting(enum vpp_matrix_e mtx_sel,
 	/*pr_info("mtx_sel:%d, mtx_csc:0x%x\n", mtx_sel, mtx_csc);*/
 }
 
+void ve_sharpness_gain_set(int sr0_gain, int sr1_gain,
+	enum wr_md_e mode, int vpp_index)
+{
+	int i;
+	int slice_max;
+	int sr0_reg = VPP_SRSHARP0_PK_FINALGAIN_HP_BP;
+	int sr1_reg = VPP_SRSHARP1_PK_FINALGAIN_HP_BP;
+
+	slice_max = get_slice_max();
+
+	if (mode == WR_VCB) {
+		for (i = SLICE0; i < slice_max; i++) {
+			WRITE_VPP_REG_BITS_S5(sr0_reg + sr_sharp_reg_ofst[i],
+				sr0_gain, 0, 16);
+			WRITE_VPP_REG_BITS_S5(sr1_reg + sr_sharp_reg_ofst[i],
+				sr1_gain, 0, 16);
+
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr0_reg + sr_sharp_reg_ofst[i], sr0_gain);
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr1_reg + sr_sharp_reg_ofst[i], sr1_gain);
+		}
+	} else if (mode == WR_DMA) {
+		for (i = SLICE0; i < slice_max; i++) {
+			VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(sr0_reg + sr_sharp_reg_ofst[i],
+				sr0_gain, 0, 16, vpp_index);
+			VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(sr1_reg + sr_sharp_reg_ofst[i],
+				sr1_gain, 0, 16, vpp_index);
+
+			pr_amve_v2("%s: vpp_index = %d\n", __func__, vpp_index);
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr0_reg + sr_sharp_reg_ofst[i], sr0_gain);
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr1_reg + sr_sharp_reg_ofst[i], sr1_gain);
+		}
+	}
+}
+
 void ve_sharpness_ctl(enum wr_md_e mode, int sr0_en,
 	int sr1_en, int vpp_index)
 {
@@ -1588,6 +1642,11 @@ void ve_sharpness_ctl(enum wr_md_e mode, int sr0_en,
 				sr0_en, 1, 1);
 			WRITE_VPP_REG_BITS_S5(sr1_reg + sr_sharp_reg_ofst[i],
 				sr1_en, 1, 1);
+
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr0_reg + sr_sharp_reg_ofst[i], sr0_en);
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr1_reg + sr_sharp_reg_ofst[i], sr1_en);
 		}
 	} else if (mode == WR_DMA) {
 		for (i = SLICE0; i < slice_max; i++) {
@@ -1595,13 +1654,13 @@ void ve_sharpness_ctl(enum wr_md_e mode, int sr0_en,
 				sr0_en, 1, 1, vpp_index);
 			VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(sr1_reg + sr_sharp_reg_ofst[i],
 				sr1_en, 1, 1, vpp_index);
+
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr0_reg + sr_sharp_reg_ofst[i], sr0_en);
+			pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
+				sr1_reg + sr_sharp_reg_ofst[i], sr1_en);
 		}
 	}
-
-	pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
-		sr0_reg + sr_sharp_reg_ofst[i], sr0_en);
-	pr_amve_v2("%s: addr = %x, val = %d\n", __func__,
-		sr1_reg + sr_sharp_reg_ofst[i], sr1_en);
 }
 
 void ve_dnlp_set(ulong *data)

drivers/media/enhancement/amvecm/amve_v2.h

@@ -78,6 +78,8 @@ int ve_vadj_misc_get(enum vadj_index_e vadj_idx,
 void ve_mtrx_setting(enum vpp_matrix_e mtx_sel,
 	int mtx_csc, int mtx_on, enum vpp_slice_e slice);
 
+void ve_sharpness_gain_set(int sr0_gain, int sr1_gain,
+	enum wr_md_e mode, int vpp_index);
 void ve_sharpness_ctl(enum wr_md_e mode, int sr0_en,
 	int sr1_en, int vpp_index);
 void ve_dnlp_set(ulong *data);

drivers/media/enhancement/amvecm/amvecm.c

@@ -1234,7 +1234,8 @@ static void vpp_backup_histgram(struct vframe_s *vf)
 	set_lum_ave(ave);
 
 	if (pr_hist) {
-		for (i = 0; i < 8; i++) {
+		pr_info("vpp_histgram data:\n");
+		for (i = 0; i < 8; i++)
 			pr_info("%d, %d, %d, %d, %d, %d, %d, %d\n",
 				vpp_hist_param.vpp_histgram[i * 8 + 0],
 				vpp_hist_param.vpp_histgram[i * 8 + 1],
@@ -1244,8 +1245,13 @@ static void vpp_backup_histgram(struct vframe_s *vf)
 				vpp_hist_param.vpp_histgram[i * 8 + 5],
 				vpp_hist_param.vpp_histgram[i * 8 + 6],
 				vpp_hist_param.vpp_histgram[i * 8 + 7]);
-			pr_info("ave = %d\n", ave);
-		}
+		pr_info("ave = %d\n", ave);
+
+		pr_info("hue/sat_histgram data:\n");
+		for (i = 0; i < 32; i++)
+			pr_info("[i] %d, %d\n",
+				vpp_hist_param.hue_histgram[i],
+				vpp_hist_param.sat_histgram[i]);
 	}
 }
 
@@ -1386,6 +1392,7 @@ void vpp_get_vframe_hist_info(struct vframe_s *vf)
 	if (chip_type_id == chip_s5 ||
 		chip_type_id == chip_t3x) {
 		get_luma_hist(vf);
+		get_cm_hist(vf);
 		return;
 	}
 
@@ -2540,6 +2547,7 @@ void amvecm_video_latch(int vpp_index)
 	bs_ct_update(vpp_index);
 	pr_amvecm_bringup_dbg("[on_vs] bs_ct done.\n");
 	dnlp_en_update(vpp_index);
+	sharpness_gain_update(vpp_index);
 #endif
 }
 

drivers/media/enhancement/amvecm/arch/vpp_regs_v2.h

@@ -770,6 +770,8 @@
 
 #define VPP_SRSHARP0_PK_NR_EN                     0x5027
 #define VPP_SRSHARP1_PK_NR_EN                     0x5227
+#define VPP_SRSHARP0_PK_FINALGAIN_HP_BP           0x5022
+#define VPP_SRSHARP1_PK_FINALGAIN_HP_BP           0x5222
 
 #define VPP_SR2_SHARP_PROC_1R                     0x5257
 #define VPP_SR2_SHARP_PROC_1R_S1                  0x7757

drivers/media/video_sink/vpp_pq_process.c

@@ -369,6 +369,17 @@ void aipq_scs_proc(struct vframe_s *vf,
 		(cur_blue_pct - pre_blue_pct) :
 		(pre_blue_pct - cur_blue_pct);
 
+	if (pq_debug[2] > 0x10) {
+		pr_info("cur_skin_hist = %lld, cur_green_hist = %lld\n",
+			cur_skin_hist, cur_green_hist);
+		pr_info("cur_blue_hist = %lld, cur_total_hist = %d\n",
+			cur_blue_hist, cur_total_hist);
+		pr_info("pre_skin/green/blue_pct = %d/%d/%d\n",
+			pre_skin_pct, pre_green_pct, pre_blue_pct);
+		pr_info("cur_skin/green/blue_pct = %d/%d/%d\n",
+			cur_skin_pct, cur_green_pct, cur_blue_pct);
+	}
+
 #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM
 	color_th = get_color_th();
 #endif
@@ -377,6 +388,8 @@ void aipq_scs_proc(struct vframe_s *vf,
 		memcpy(out, cfg[pre_top_one], sizeof(int) * SCENES_VALUE);
 		scene_prob[0] = top_one;
 		scene_prob[1] = top_one_prob;
+		if (pq_debug[2] > 0x10)
+			pr_info("pre_top_one == top_one\n");
 	} else if (((pre_top_one == top_two) && (top_two_prob > 1000)) ||
 			((pre_top_one == top_three) && (top_three_prob > 1000))) {
 		memcpy(out, cfg[pre_top_one], sizeof(int) * SCENES_VALUE);
@@ -388,12 +401,25 @@ void aipq_scs_proc(struct vframe_s *vf,
 			scene_prob[0] = top_three;
 			scene_prob[1] = top_three_prob;
 		}
+
+		if (pq_debug[2] > 0x10) {
+			pr_info("top_two = %d, top_two_prob = %d\n",
+				top_two, top_two_prob);
+			pr_info("top_three = %d, top_three_prob = %d\n",
+				top_two, top_two_prob);
+		}
 	} else if ((diff_skin_pct + diff_green_pct + diff_blue_pct < color_th) &&
 			    (pre_top_one >= 0)) {
 		memcpy(out, cfg[pre_top_one], sizeof(int) * SCENES_VALUE);
+		if (pq_debug[2] > 0x10)
+			pr_info("pre_top_one = %d, color_th = %d\n",
+				pre_top_one, color_th);
 	} else if ((top_one == 1) && (pre_top_one == 3) && (pre_blue_pct > 500) &&
 		(pre_blue_pct < cur_blue_pct)) {
 		memcpy(out, cfg[pre_top_one], sizeof(int) * SCENES_VALUE);
+		if (pq_debug[2] > 0x10)
+			pr_info("pre_blue_pct = %d, cur_blue_pct = %d\n",
+				pre_blue_pct, cur_blue_pct);
 	} else {
 		if (pq_debug[2] == 0x8) {
 			pr_info("pre_top_one = %d, top_one = %d, top_one_prob = %d, diff_skin_pct = %d, diff_green_pct = %d, diff_blue_pct = %d\n",

include/linux/amlogic/media/amvecm/amvecm.h

@@ -111,6 +111,7 @@ bool is_hdmi_ll_as_hdr10(void);
  *#define VPP_VADJ1_BLMINUS_EN        (1 << 1)
  *#define VPP_VADJ1_EN                (1 << 0)
  */
+#define SHARPNESS_GAIN_UPDATE       BIT(20)
 #define FLAG_GAMMA_TABLE_EN_SUB     BIT(19)
 #define FLAG_GAMMA_TABLE_DIS_SUB    BIT(18)
 #define FLAG_GAMMA_TABLE_R_SUB      BIT(17)