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hdmitx: adjust the hdmiphy_ctrl5 setting [1/1]

Browse Source 
PD#SWPL-74148

Problem:
During the suspend, the hdmiphy_ctrl5 setting is 0x800, and it will
enable the clock directly from the HPLL VCO

Solution:
Adjust the hdmiphy_ctrl5 setting when set phy

Verify:
boreal

Change-Id: I324086cf05fef933ee0d238dc4f7997958a5b45b
Signed-off-by: Wenjie Qiao <wenjie.qiao@amlogic.com>
This commit is contained in:
Wenjie Qiao
2022-09-01 11:13:25 +08:00
committed by Wanwei Jiang
parent 82e39409d1
commit 093b0ff4f4
5 changed files with 18 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+6 -6
View File
@@ -569,35 +569,35 @@ void set_phy_by_mode_g12(unsigned int mode)
{
switch (mode) {
case HDMI_PHYPARA_6G: /* 5.94Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb76d4);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case HDMI_PHYPARA_4p5G: /* 4.5Gbps*/
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65d4);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case HDMI_PHYPARA_3p7G: /* 3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb6272);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case HDMI_PHYPARA_270M: /* SD format, 480p/576p, 270Mbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb5252);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case HDMI_PHYPARA_DEF: /* less than 2.97G */
default:
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
}
}
drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sc2.c
+3 -3
View File
@@ -357,24 +357,24 @@ void set_phy_by_mode_sc2(unsigned int mode)
case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
case HDMI_PHYPARA_4p5G:
case HDMI_PHYPARA_3p7G:
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
/* for hdmi_rext use the 1.3k resistor */
if (mode == HDMI_PHYPARA_6G && hdev->hdmi_rext == 1300)
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb6584);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
break;
case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
case HDMI_PHYPARA_DEF:
default:
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
break;
}
}
drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_sm1.c
+3 -3
View File
@@ -14,21 +14,21 @@ void set_phy_by_mode_sm1(unsigned int mode)
case HDMI_PHYPARA_6G: /* 5.94Gbps */
case HDMI_PHYPARA_4p5G: /* 4.5Gbps*/
case HDMI_PHYPARA_3p7G: /* 3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb42a2);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case HDMI_PHYPARA_270M: /* SD format, 480p/576p, 270Mbps */
case HDMI_PHYPARA_DEF: /* less than 2.97G */
default:
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4252);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
}
}
drivers/media/vout/hdmitx/hdmi_tx_20/hw/hw_tm2.c
+3 -3
View File
@@ -23,21 +23,21 @@ void set_phy_by_mode_tm2(unsigned int mode)
case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
case HDMI_PHYPARA_4p5G:
case HDMI_PHYPARA_3p7G:
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x0000080b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33EB65c4);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb42a5);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
case HDMI_PHYPARA_DEF:
default:
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
}
}
drivers/media/vout/hdmitx21/hw/hw_t7.c
+3 -3
View File
@@ -352,21 +352,21 @@ void set21_phy_by_mode_t7(u32 mode)
case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
case HDMI_PHYPARA_4p5G:
case HDMI_PHYPARA_3p7G:
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x00000003);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x00000003);
break;
case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
case HDMI_PHYPARA_DEF:
default:
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x00000003);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x00000003);
break;
}
}