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lcd: add pre_de_h timing for tconless panel [2/2]

Browse Source 
PD#SWPL-229200

Problem:
need support pre_de_h timing for tconless panel

Solution:
add pre_de_h timing support for tconless panel

Verify:
bc302

Change-Id: I550086327c50cd1e833050837bc63ab86cd5f686
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2025-08-26 11:02:26 +08:00
committed by gerrit autosubmit
parent f512e972c7
commit 10f4b94de7
5 changed files with 65 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vout/lcd/lcd_clk/lcd_clk_utils.c
+35 -33
View File
@@ -1683,45 +1683,16 @@ int lcd_clk_config_print_dft(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
{
struct lcd_clk_config_s *cconf = NULL;
struct lcd_pll_config_s *pll_config = NULL;
int i = 0;
int pll_num = 1, i = 0;
int n, len = 0;
cconf = get_lcd_clk_config(pdrv);
if (!cconf || !cconf->data)
return -1;
n = lcd_debug_info_len(len + offset);
len += snprintf((buf + len), n,
"[%d]: clk config:\n"
" phy_clk: %lldHz\n"
" edp_div0: %d\n"
" edp_div1: %d\n"
" xd: %d\n"
" fout: %uHz\n"
" pll_mode: 0x%x\n"
" pll_tcon_div_sel: %d\n"
" vclk_sel: %d\n",
pdrv->index, cconf->phy_clk,
edp_div0_table[cconf->edp_div0], edp_div1_table[cconf->edp_div1],
cconf->xd, cconf->fout, cconf->pll_mode,
cconf->pll_tcon_div_sel,
cconf->data->vclk_sel);
if (cconf->data->ss_support) {
n = lcd_debug_info_len(len + offset);
len += snprintf((buf + len), n,
"[%d]: clk config:\n"
" ss_level: %d\n"
" ss_dep_sel: %d\n"
" ss_str_m: %d\n"
" ss_ppm: %d\n"
" ss_freq: %d\n"
" ss_mode: %d\n"
" ss_en: %d\n\n",
pdrv->index, cconf->ss_level,
cconf->ss_dep_sel, cconf->ss_str_m, cconf->ss_ppm,
cconf->ss_freq, cconf->ss_mode, cconf->ss_en);
}
for (i = 0; i < cconf->pll_conf_num; i++) {
if (cconf->pll_mode & LCD_PLL_MODE_DUAL_PLL)
pll_num = cconf->pll_conf_num;
for (i = 0; i < pll_num; i++) {
pll_config = &cconf->pll_config[i];
n = lcd_debug_info_len(len + offset);
len += snprintf((buf + len), n,
@@ -1748,6 +1719,37 @@ int lcd_clk_config_print_dft(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
lcd_clk_div_table[pll_config->div_sel].name,
pll_config->div_sel, pll_config->pll_div_fout);
}
n = lcd_debug_info_len(len + offset);
len += snprintf((buf + len), n,
"[%d]: clk config:\n"
" pll_mode: 0x%x\n"
" pll_tcon_div_sel: %d\n"
" phy_clk: %lldHz\n"
" edp_div0: %d\n"
" edp_div1: %d\n"
" xd: %d\n"
" fout: %uHz\n"
" vclk_sel: %d\n",
pdrv->index, cconf->pll_mode,
cconf->pll_tcon_div_sel, cconf->phy_clk,
edp_div0_table[cconf->edp_div0], edp_div1_table[cconf->edp_div1],
cconf->xd, cconf->fout, cconf->data->vclk_sel);
if (cconf->data->ss_support) {
n = lcd_debug_info_len(len + offset);
len += snprintf((buf + len), n,
" ss_level: %d\n"
" ss_dep_sel: %d\n"
" ss_str_m: %d\n"
" ss_ppm: %d\n"
" ss_freq: %d\n"
" ss_mode: %d\n"
" ss_en: %d\n\n",
cconf->ss_level,
cconf->ss_dep_sel, cconf->ss_str_m, cconf->ss_ppm,
cconf->ss_freq, cconf->ss_mode, cconf->ss_en);
}
return len;
}
drivers/media/vout/lcd/lcd_venc/lcd_venc_dft.c
+10 -9
View File
@@ -207,7 +207,7 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
{
struct lcd_config_s *pconf = &pdrv->curr_dev->dev_cfg;
unsigned int hstart, hend, vstart, vend;
unsigned int pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int pre_hde, pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
hstart = pconf->timing.hstart;
hend = pconf->timing.hend;
@@ -222,21 +222,20 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE, vend);
if (pconf->basic.lcd_type == LCD_P2P ||
pconf->basic.lcd_type == LCD_MLVDS) {
pre_hde = pconf->timing.pre_de_h ? pconf->timing.pre_de_h : PRE_DE_DELAY;
pre_de_hs = pconf->timing.hstart + pre_hde;
pre_de_he = pconf->timing.act_timing.h_active - 1 + pre_de_hs;
switch (pdrv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
pre_vde = pconf->timing.pre_de_v ? pconf->timing.pre_de_v : 5;
pre_de_vs = vstart - pre_vde;
pre_de_vs = pconf->timing.vstart - pre_vde;
pre_de_ve = pre_de_vs + 4;
pre_de_hs = hstart + PRE_DE_DELAY;
pre_de_he = pconf->timing.act_timing.h_active - 1 + pre_de_hs;
break;
default:
pre_vde = pconf->timing.pre_de_v ? pconf->timing.pre_de_v : 8;
pre_de_vs = vstart - pre_vde;
pre_de_vs = pconf->timing.vstart - pre_vde;
pre_de_ve = pconf->timing.act_timing.v_active + pre_de_vs;
pre_de_hs = hstart + PRE_DE_DELAY;
pre_de_he = pconf->timing.act_timing.h_active - 1 + pre_de_hs;
break;
}
lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_BLINE, pre_de_vs);
@@ -415,6 +414,10 @@ static int lcd_venc_reg_dump(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
ENCL_VIDEO_VSO_END,
ENCL_VIDEO_VSO_BLINE,
ENCL_VIDEO_VSO_ELINE,
ENCL_VIDEO_H_PRE_DE_BEGIN,
ENCL_VIDEO_H_PRE_DE_END,
ENCL_VIDEO_V_PRE_DE_BLINE,
ENCL_VIDEO_V_PRE_DE_ELINE,
ENCL_VIDEO_RGBIN_CTRL,
L_GAMMA_CNTL_PORT,
L_RGB_BASE_ADDR,
@@ -428,8 +431,6 @@ static int lcd_venc_reg_dump(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
};
switch (pdrv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
case LCD_CHIP_T5:
case LCD_CHIP_T5D:
case LCD_CHIP_TXHD2:
drivers/media/vout/lcd/lcd_venc/lcd_venc_t3x.c
+6 -3
View File
@@ -256,7 +256,7 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
struct lcd_config_s *pconf = &pdrv->curr_dev->dev_cfg;
unsigned int hstart, hend, vstart, vend, h_period, v_period;
unsigned int offset;
unsigned int pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int pre_hde, pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int hs_hs_addr, hs_he_addr, vs_vs_addr, vs_ve_addr, vs_hs_addr, vs_he_addr;
unsigned int ppc, slice, p2s_px_dly;
unsigned int hde_px_bgn, hde_px_end;
@@ -321,9 +321,10 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
if (pconf->basic.lcd_type == LCD_P2P ||
pconf->basic.lcd_type == LCD_MLVDS) {
pre_vde = pconf->timing.pre_de_v ? pconf->timing.pre_de_v : 16;
pre_de_vs = vstart - pre_vde;
pre_hde = pconf->timing.pre_de_h ? pconf->timing.pre_de_h : 6;
pre_de_vs = pconf->timing.vstart - pre_vde;
pre_de_ve = pconf->timing.act_timing.v_active + pre_de_vs;
pre_de_hs = hstart + 6;
pre_de_hs = pconf->timing.hstart + pre_hde;
pre_de_he = pconf->timing.act_timing.h_active + pre_de_hs;
lcd_vcbus_setb(ENCL_VIDEO_V_PRE_DE_LN_RNG + offset, pre_de_vs, 16, 16);
lcd_vcbus_setb(ENCL_VIDEO_V_PRE_DE_LN_RNG + offset, pre_de_ve, 0, 16);
@@ -601,6 +602,8 @@ static int lcd_venc_reg_dump(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
ENCL_VIDEO_HSO_PX_RNG,
ENCL_VIDEO_VSO_PX_RNG,
ENCL_VIDEO_VSO_LN_RNG,
ENCL_VIDEO_H_PRE_DE_PX_RNG,
ENCL_VIDEO_V_PRE_DE_LN_RNG,
ENCL_INBUF_CNTL0_T3X,
ENCL_INBUF_CNTL1,
VPU_DISP_VIU0_CTRL,
drivers/media/vout/lcd/lcd_venc/lcd_venc_t6x.c
+6 -4
View File
@@ -257,7 +257,7 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
{
struct lcd_config_s *pconf = &pdrv->curr_dev->dev_cfg;
unsigned int hstart, hend, vstart, vend, h_period, v_period;
unsigned int pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int pre_hde, pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int hs_hs_addr, hs_he_addr, vs_vs_addr, vs_ve_addr, vs_hs_addr, vs_he_addr;
unsigned int ppc, slice, p2s_px_dly;
unsigned int hde_px_bgn, hde_px_end;
@@ -321,9 +321,10 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
if (pconf->basic.lcd_type == LCD_P2P ||
pconf->basic.lcd_type == LCD_MLVDS) {
pre_vde = pconf->timing.pre_de_v ? pconf->timing.pre_de_v : 16;
pre_de_vs = vstart - pre_vde;
pre_hde = pconf->timing.pre_de_h ? pconf->timing.pre_de_h : 6;
pre_de_vs = pconf->timing.vstart - pre_vde;
pre_de_ve = pconf->timing.act_timing.v_active + pre_de_vs;
pre_de_hs = hstart + 6;
pre_de_hs = pconf->timing.hstart + pre_hde;
pre_de_he = pconf->timing.act_timing.h_active + pre_de_hs;
lcd_vcbus_setb(ENCL_VIDEO_V_PRE_DE_LN_RNG_T6X, pre_de_vs, 16, 16);
lcd_vcbus_setb(ENCL_VIDEO_V_PRE_DE_LN_RNG_T6X, pre_de_ve, 0, 16);
@@ -603,7 +604,8 @@ static int lcd_venc_reg_dump(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
{ENCL_VIDEO_HSO_PX_RNG_T6X, "ENCL_VIDEO_HSO_PX_RNG "},
{ENCL_VIDEO_VSO_PX_RNG_T6X, "ENCL_VIDEO_VSO_PX_RNG "},
{ENCL_VIDEO_VSO_LN_RNG_T6X, "ENCL_VIDEO_VSO_LN_RNG "},
{ENCL_VIDEO_H_PRE_DE_PX_RNG_T6X, "ENCL_VIDEO_H_PRE_DE_PX_RNG"},
{ENCL_VIDEO_H_PRE_DE_PX_RNG_T6X, "ENCL_VID_H_PRE_DE_PX_RNG"},
{ENCL_VIDEO_V_PRE_DE_LN_RNG_T6X, "ENCL_VID_V_PRE_DE_LN_RNG"},
{ENCL_DBG_PX_LN_RST_T6X, "ENCL_DBG_PX_LN_RST "},
{ENCL_DBG_PX_LN_INT_T6X, "ENCL_DBG_PX_LN_INT "}
};
drivers/media/vout/lcd/lcd_venc/lcd_venc_t7.c
+8 -3
View File
@@ -331,7 +331,7 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
struct lcd_config_s *pconf = &pdrv->curr_dev->dev_cfg;
unsigned int hstart, hend, vstart, vend;
unsigned int offset;
unsigned int pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
unsigned int pre_hde, pre_vde, pre_de_vs, pre_de_ve, pre_de_hs, pre_de_he;
offset = pdrv->data->offset_venc[pdrv->index];
hstart = pconf->timing.hstart;
@@ -348,9 +348,10 @@ static void lcd_venc_set_timing(struct aml_lcd_drv_s *pdrv)
if (pconf->basic.lcd_type == LCD_P2P ||
pconf->basic.lcd_type == LCD_MLVDS) {
pre_vde = pconf->timing.pre_de_v ? pconf->timing.pre_de_v : 8;
pre_de_vs = vstart - pre_vde;
pre_hde = pconf->timing.pre_de_h ? pconf->timing.pre_de_h : PRE_DE_DELAY;
pre_de_vs = pconf->timing.vstart - pre_vde;
pre_de_ve = pconf->timing.act_timing.v_active + pre_de_vs;
pre_de_hs = hstart + PRE_DE_DELAY;
pre_de_hs = pconf->timing.hstart + pre_hde;
pre_de_he = pconf->timing.act_timing.h_active - 1 + pre_de_hs;
lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_BLINE + offset, pre_de_vs);
lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_ELINE + offset, pre_de_ve);
@@ -722,6 +723,10 @@ static int lcd_venc_reg_dump(struct aml_lcd_drv_s *pdrv, char *buf, int offset)
ENCL_VIDEO_VSO_END,
ENCL_VIDEO_VSO_BLINE,
ENCL_VIDEO_VSO_ELINE,
ENCL_VIDEO_H_PRE_DE_BEGIN,
ENCL_VIDEO_H_PRE_DE_END,
ENCL_VIDEO_V_PRE_DE_BLINE,
ENCL_VIDEO_V_PRE_DE_ELINE,
ENCL_VIDEO_RGBIN_CTRL,
ENCL_INBUF_CNTL0,
ENCL_INBUF_CNTL1,